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girish44961712006-11-22 11:47:19 -08001/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
Santwona Behera9d587972010-05-20 10:19:34 -070022 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
girish44961712006-11-22 11:47:19 -080023 */
24
speera3c5bd62007-01-30 11:29:19 -080025#include <sys/nxge/nxge_impl.h>
26#include <sys/nxge/nxge_mac.h>
speer678453a2008-04-27 19:50:44 -070027#include <sys/nxge/nxge_hio.h>
girish44961712006-11-22 11:47:19 -080028
Michael Speer952a2462009-03-11 16:27:24 -070029/*
30 * Local defines for FWARC 2006/556
31 */
32#define NXGE_NIU_TDMA_PROP_LEN 2
33#define NXGE_NIU_RDMA_PROP_LEN 2
34#define NXGE_NIU_0_INTR_PROP_LEN 19
35#define NXGE_NIU_1_INTR_PROP_LEN 17
36
37/*
38 * Local functions.
39 */
girish44961712006-11-22 11:47:19 -080040static void nxge_get_niu_property(dev_info_t *, niu_type_t *);
sd7746814ea4bb2006-12-22 12:42:28 -080041static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t);
girish44961712006-11-22 11:47:19 -080042static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t);
43static void nxge_use_cfg_neptune_properties(p_nxge_t);
44static void nxge_use_cfg_dma_config(p_nxge_t);
45static void nxge_use_cfg_vlan_class_config(p_nxge_t);
46static void nxge_use_cfg_mac_class_config(p_nxge_t);
47static void nxge_use_cfg_class_config(p_nxge_t);
48static void nxge_use_cfg_link_cfg(p_nxge_t);
girish44961712006-11-22 11:47:19 -080049static void nxge_set_hw_dma_config(p_nxge_t);
50static void nxge_set_hw_vlan_class_config(p_nxge_t);
51static void nxge_set_hw_mac_class_config(p_nxge_t);
52static void nxge_set_hw_class_config(p_nxge_t);
girish44961712006-11-22 11:47:19 -080053static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t);
speera3c5bd62007-01-30 11:29:19 -080054static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t,
girish44961712006-11-22 11:47:19 -080055 uint8_t, int *);
davemq59ac0c12007-07-25 18:20:14 -070056static void nxge_init_mmac(p_nxge_t, boolean_t);
speer678453a2008-04-27 19:50:44 -070057static void nxge_set_rdc_intr_property(p_nxge_t);
girish44961712006-11-22 11:47:19 -080058
speera3c5bd62007-01-30 11:29:19 -080059uint32_t nxge_use_hw_property = 1;
60uint32_t nxge_groups_per_port = 2;
girish44961712006-11-22 11:47:19 -080061
speera3c5bd62007-01-30 11:29:19 -080062extern uint32_t nxge_use_partition;
63extern uint32_t nxge_dma_obp_props_only;
girish44961712006-11-22 11:47:19 -080064
speera3c5bd62007-01-30 11:29:19 -080065extern uint_t nxge_rx_intr(void *, void *);
66extern uint_t nxge_tx_intr(void *, void *);
67extern uint_t nxge_mif_intr(void *, void *);
68extern uint_t nxge_mac_intr(void *, void *);
69extern uint_t nxge_syserr_intr(void *, void *);
girish44961712006-11-22 11:47:19 -080070extern void *nxge_list;
71
72#define NXGE_SHARED_REG_SW_SIM
73
74#ifdef NXGE_SHARED_REG_SW_SIM
75uint64_t global_dev_ctrl = 0;
76#endif
77
78#define MAX_SIBLINGS NXGE_MAX_PORTS
79
speera3c5bd62007-01-30 11:29:19 -080080extern uint32_t nxge_rbr_size;
81extern uint32_t nxge_rcr_size;
82extern uint32_t nxge_tx_ring_size;
83extern uint32_t nxge_rbr_spare_size;
girish44961712006-11-22 11:47:19 -080084
speera3c5bd62007-01-30 11:29:19 -080085extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);
girish44961712006-11-22 11:47:19 -080086
87static uint8_t p2_tx_fair[2] = {12, 12};
88static uint8_t p2_tx_equal[2] = {12, 12};
89static uint8_t p4_tx_fair[4] = {6, 6, 6, 6};
90static uint8_t p4_tx_equal[4] = {6, 6, 6, 6};
91static uint8_t p2_rx_fair[2] = {8, 8};
92static uint8_t p2_rx_equal[2] = {8, 8};
girish44961712006-11-22 11:47:19 -080093static uint8_t p4_rx_fair[4] = {4, 4, 4, 4};
94static uint8_t p4_rx_equal[4] = {4, 4, 4, 4};
95
96static uint8_t p2_rdcgrp_fair[2] = {4, 4};
97static uint8_t p2_rdcgrp_equal[2] = {4, 4};
98static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1};
99static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2};
100static uint8_t p2_rdcgrp_cls[2] = {1, 1};
101static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1};
102
davemq59ac0c12007-07-25 18:20:14 -0700103static uint8_t rx_4_1G[4] = {4, 4, 4, 4};
104static uint8_t rx_2_10G[2] = {8, 8};
105static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2};
106static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2};
107static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2};
108
109static uint8_t tx_4_1G[4] = {6, 6, 6, 6};
110static uint8_t tx_2_10G[2] = {12, 12};
111static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2};
112static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4};
113static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4};
114
girish44961712006-11-22 11:47:19 -0800115typedef enum {
116 DEFAULT = 0,
117 EQUAL,
118 FAIR,
119 CUSTOM,
120 CLASSIFY,
121 L2_CLASSIFY,
122 L3_DISTRIBUTE,
123 L3_CLASSIFY,
124 L3_TCAM,
125 CONFIG_TOKEN_NONE
126} config_token_t;
127
128static char *token_names[] = {
129 "default",
130 "equal",
131 "fair",
132 "custom",
133 "classify",
134 "l2_classify",
135 "l3_distribute",
136 "l3_classify",
137 "l3_tcam",
138 "none",
139};
140
141void nxge_virint_regs_dump(p_nxge_t nxgep);
142
143void
144nxge_virint_regs_dump(p_nxge_t nxgep)
145{
speera3c5bd62007-01-30 11:29:19 -0800146 npi_handle_t handle;
girish44961712006-11-22 11:47:19 -0800147
148 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump"));
149 handle = NXGE_DEV_NPI_HANDLE(nxgep);
150 (void) npi_vir_dump_pio_fzc_regs_one(handle);
151 (void) npi_vir_dump_ldgnum(handle);
152 (void) npi_vir_dump_ldsv(handle);
153 (void) npi_vir_dump_imask0(handle);
154 (void) npi_vir_dump_sid(handle);
155 (void) npi_mac_dump_regs(handle, nxgep->function_num);
156 (void) npi_ipp_dump_regs(handle, nxgep->function_num);
157 (void) npi_fflp_dump_regs(handle);
158 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump"));
159}
160
161/*
162 * For now: we hard coded the DMA configurations.
163 * and assume for one partition only.
164 *
165 * OBP. Then OBP will pass this partition's
166 * Neptune configurations to fcode to create
167 * properties for them.
168 *
169 * Since Neptune(PCI-E) and NIU (Niagara-2) has
170 * different bus interfaces, the driver needs
171 * to know which bus it is connected to.
172 * Ravinder suggested: create a device property.
173 * In partitioning environment, we cannot
174 * use .conf file (need to check). If conf changes,
175 * need to reboot the system.
176 * The following function assumes that we will
177 * retrieve its properties from a virtualized nexus driver.
178 */
179
girish44961712006-11-22 11:47:19 -0800180nxge_status_t
181nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result)
182{
speera3c5bd62007-01-30 11:29:19 -0800183 nxge_status_t status = NXGE_OK;
girish44961712006-11-22 11:47:19 -0800184 int instance;
speera3c5bd62007-01-30 11:29:19 -0800185 p_nxge_t nxgep;
186
girish44961712006-11-22 11:47:19 -0800187#ifndef NXGE_SHARED_REG_SW_SIM
188 npi_handle_t handle;
189 uint16_t sr16, cr16;
190#endif
191 instance = ddi_get_instance(dip);
speera3c5bd62007-01-30 11:29:19 -0800192 NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance));
193
girish44961712006-11-22 11:47:19 -0800194 if (nxge_list == NULL) {
195 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700196 "nxge_cntlops: nxge_list null"));
girish44961712006-11-22 11:47:19 -0800197 return (NXGE_ERROR);
198 }
199 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
200 if (nxgep == NULL) {
201 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700202 "nxge_cntlops: nxgep null"));
girish44961712006-11-22 11:47:19 -0800203 return (NXGE_ERROR);
204 }
205#ifndef NXGE_SHARED_REG_SW_SIM
206 handle = nxgep->npi_reg_handle;
207#endif
208 switch (ctlop) {
209 case NXGE_CTLOPS_NIUTYPE:
210 nxge_get_niu_property(dip, (niu_type_t *)result);
211 return (status);
speera3c5bd62007-01-30 11:29:19 -0800212
girish44961712006-11-22 11:47:19 -0800213 case NXGE_CTLOPS_GET_SHARED_REG:
214#ifdef NXGE_SHARED_REG_SW_SIM
215 *(uint64_t *)result = global_dev_ctrl;
216 return (0);
217#else
218 status = npi_dev_func_sr_sr_get(handle, &sr16);
219 *(uint16_t *)result = sr16;
220 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700221 "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG"));
girish44961712006-11-22 11:47:19 -0800222 return (0);
223#endif
224
225 case NXGE_CTLOPS_SET_SHARED_REG_LOCK:
226#ifdef NXGE_SHARED_REG_SW_SIM
speera3c5bd62007-01-30 11:29:19 -0800227 global_dev_ctrl = *(uint64_t *)arg;
girish44961712006-11-22 11:47:19 -0800228 return (0);
229#else
230 status = NPI_FAILURE;
231 while (status != NPI_SUCCESS)
232 status = npi_dev_func_sr_lock_enter(handle);
233
234 sr16 = *(uint16_t *)arg;
235 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
236 status = npi_dev_func_sr_lock_free(handle);
237 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700238 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
girish44961712006-11-22 11:47:19 -0800239 return (0);
240#endif
241
242 case NXGE_CTLOPS_UPDATE_SHARED_REG:
243#ifdef NXGE_SHARED_REG_SW_SIM
244 global_dev_ctrl |= *(uint64_t *)arg;
245 return (0);
246#else
247 status = NPI_FAILURE;
248 while (status != NPI_SUCCESS)
249 status = npi_dev_func_sr_lock_enter(handle);
250 status = npi_dev_func_sr_sr_get(handle, &sr16);
251 sr16 |= *(uint16_t *)arg;
252 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
253 status = npi_dev_func_sr_lock_free(handle);
254 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700255 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
girish44961712006-11-22 11:47:19 -0800256 return (0);
girish44961712006-11-22 11:47:19 -0800257#endif
258
259 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL:
260#ifdef NXGE_SHARED_REG_SW_SIM
261 global_dev_ctrl |= *(uint64_t *)arg;
262 return (0);
263#else
264 status = npi_dev_func_sr_sr_get(handle, &sr16);
265 cr16 = *(uint16_t *)arg;
266 sr16 &= ~cr16;
267 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
268 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700269 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
girish44961712006-11-22 11:47:19 -0800270 return (0);
271#endif
272
273 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG:
274#ifdef NXGE_SHARED_REG_SW_SIM
275 global_dev_ctrl |= *(uint64_t *)arg;
276 return (0);
277#else
278 status = NPI_FAILURE;
279 while (status != NPI_SUCCESS)
280 status = npi_dev_func_sr_lock_enter(handle);
281 status = npi_dev_func_sr_sr_get(handle, &sr16);
282 cr16 = *(uint16_t *)arg;
283 sr16 &= ~cr16;
284 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
285 status = npi_dev_func_sr_lock_free(handle);
286 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700287 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
girish44961712006-11-22 11:47:19 -0800288 return (0);
289#endif
290
291 case NXGE_CTLOPS_GET_LOCK_BLOCK:
292#ifdef NXGE_SHARED_REG_SW_SIM
293 global_dev_ctrl |= *(uint64_t *)arg;
294 return (0);
295#else
296 status = NPI_FAILURE;
297 while (status != NPI_SUCCESS)
speera3c5bd62007-01-30 11:29:19 -0800298 status = npi_dev_func_sr_lock_enter(handle);
girish44961712006-11-22 11:47:19 -0800299 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700300 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK"));
girish44961712006-11-22 11:47:19 -0800301 return (0);
302#endif
303 case NXGE_CTLOPS_GET_LOCK_TRY:
304#ifdef NXGE_SHARED_REG_SW_SIM
305 global_dev_ctrl |= *(uint64_t *)arg;
306 return (0);
307#else
308 status = npi_dev_func_sr_lock_enter(handle);
309 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700310 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY"));
girish44961712006-11-22 11:47:19 -0800311 if (status == NPI_SUCCESS)
312 return (NXGE_OK);
313 else
314 return (NXGE_ERROR);
315#endif
316 case NXGE_CTLOPS_FREE_LOCK:
317#ifdef NXGE_SHARED_REG_SW_SIM
318 global_dev_ctrl |= *(uint64_t *)arg;
319 return (0);
320#else
321 status = npi_dev_func_sr_lock_free(handle);
322 NXGE_DEBUG_MSG((NULL, VIR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700323 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE"));
speera3c5bd62007-01-30 11:29:19 -0800324 if (status == NPI_SUCCESS)
girish44961712006-11-22 11:47:19 -0800325 return (NXGE_OK);
326 else
327 return (NXGE_ERROR);
328#endif
329
330 default:
331 status = NXGE_ERROR;
332 }
333
334 return (status);
335}
336
337void
338nxge_common_lock_get(p_nxge_t nxgep)
339{
340 uint32_t status = NPI_FAILURE;
341 npi_handle_t handle;
342
343#if defined(NXGE_SHARE_REG_SW_SIM)
344 return;
345#endif
346 handle = nxgep->npi_reg_handle;
347 while (status != NPI_SUCCESS)
348 status = npi_dev_func_sr_lock_enter(handle);
girish44961712006-11-22 11:47:19 -0800349}
350
girish44961712006-11-22 11:47:19 -0800351void
352nxge_common_lock_free(p_nxge_t nxgep)
353{
354 npi_handle_t handle;
speera3c5bd62007-01-30 11:29:19 -0800355
girish44961712006-11-22 11:47:19 -0800356#if defined(NXGE_SHARE_REG_SW_SIM)
357 return;
358#endif
359 handle = nxgep->npi_reg_handle;
360 (void) npi_dev_func_sr_lock_free(handle);
361}
362
speer56d930a2007-05-08 14:19:59 -0700363
girish44961712006-11-22 11:47:19 -0800364static void
365nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type)
366{
speera3c5bd62007-01-30 11:29:19 -0800367 uchar_t *prop_val;
368 uint_t prop_len;
girish44961712006-11-22 11:47:19 -0800369
davemq59ac0c12007-07-25 18:20:14 -0700370 *niu_type = NIU_TYPE_NONE;
girish44961712006-11-22 11:47:19 -0800371 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0,
misaki52ccf842008-06-20 15:53:36 -0700372 "niu-type", (uchar_t **)&prop_val,
373 &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -0800374 if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) {
375 *niu_type = N2_NIU;
376 }
377 ddi_prop_free(prop_val);
378 }
379}
380
381static config_token_t
382nxge_get_config_token(char *prop)
383{
384 config_token_t token = DEFAULT;
speera3c5bd62007-01-30 11:29:19 -0800385
girish44961712006-11-22 11:47:19 -0800386 while (token < CONFIG_TOKEN_NONE) {
387 if (strncmp(prop, token_names[token], 4) == 0)
388 break;
389 token++;
390 }
391 return (token);
392}
393
girish44961712006-11-22 11:47:19 -0800394/* per port */
395
396static nxge_status_t
397nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token,
speera3c5bd62007-01-30 11:29:19 -0800398 dev_info_t *s_dip[])
girish44961712006-11-22 11:47:19 -0800399{
400 nxge_status_t status = NXGE_OK;
401 int ddi_status;
402 int num_ports = nxgep->nports;
403 int port, bits, j;
404 uint8_t start_grp = 0, num_grps = 0;
405 p_nxge_param_t param_arr;
406 uint32_t grp_bitmap[MAX_SIBLINGS];
407 int custom_start_grp[MAX_SIBLINGS];
408 int custom_num_grp[MAX_SIBLINGS];
409 uint8_t bad_config = B_FALSE;
girish44961712006-11-22 11:47:19 -0800410 char *start_prop, *num_prop, *cfg_prop;
411
412 start_grp = 0;
413 param_arr = nxgep->param_arr;
girish44961712006-11-22 11:47:19 -0800414 start_prop = param_arr[param_rdc_grps_start].fcode_name;
415 num_prop = param_arr[param_rx_rdc_grps].fcode_name;
416
417 switch (token) {
speera3c5bd62007-01-30 11:29:19 -0800418 case FAIR:
419 cfg_prop = "fair";
420 for (port = 0; port < num_ports; port++) {
421 custom_num_grp[port] =
misaki52ccf842008-06-20 15:53:36 -0700422 (num_ports == 4) ?
423 p4_rdcgrp_fair[port] :
424 p2_rdcgrp_fair[port];
speera3c5bd62007-01-30 11:29:19 -0800425 custom_start_grp[port] = start_grp;
426 start_grp += custom_num_grp[port];
427 }
girish44961712006-11-22 11:47:19 -0800428 break;
429
speera3c5bd62007-01-30 11:29:19 -0800430 case EQUAL:
431 cfg_prop = "equal";
432 for (port = 0; port < num_ports; port++) {
433 custom_num_grp[port] =
misaki52ccf842008-06-20 15:53:36 -0700434 (num_ports == 4) ?
435 p4_rdcgrp_equal[port] :
436 p2_rdcgrp_equal[port];
speera3c5bd62007-01-30 11:29:19 -0800437 custom_start_grp[port] = start_grp;
438 start_grp += custom_num_grp[port];
439 }
440 break;
441
442
443 case CLASSIFY:
444 cfg_prop = "classify";
445 for (port = 0; port < num_ports; port++) {
446 custom_num_grp[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700447 p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port];
speera3c5bd62007-01-30 11:29:19 -0800448 custom_start_grp[port] = start_grp;
449 start_grp += custom_num_grp[port];
450 }
451 break;
452
453 case CUSTOM:
454 cfg_prop = "custom";
455 /* See if it is good config */
456 num_grps = 0;
457 for (port = 0; port < num_ports; port++) {
458 custom_start_grp[port] =
misaki52ccf842008-06-20 15:53:36 -0700459 ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port],
460 DDI_PROP_DONTPASS, start_prop, -1);
speera3c5bd62007-01-30 11:29:19 -0800461 if ((custom_start_grp[port] == -1) ||
misaki52ccf842008-06-20 15:53:36 -0700462 (custom_start_grp[port] >=
463 NXGE_MAX_RDC_GRPS)) {
speera3c5bd62007-01-30 11:29:19 -0800464 bad_config = B_TRUE;
465 break;
466 }
467 custom_num_grp[port] = ddi_prop_get_int(
misaki52ccf842008-06-20 15:53:36 -0700468 DDI_DEV_T_NONE,
469 s_dip[port],
470 DDI_PROP_DONTPASS,
471 num_prop, -1);
speera3c5bd62007-01-30 11:29:19 -0800472
473 if ((custom_num_grp[port] == -1) ||
misaki52ccf842008-06-20 15:53:36 -0700474 (custom_num_grp[port] >
475 NXGE_MAX_RDC_GRPS) ||
476 ((custom_num_grp[port] +
477 custom_start_grp[port]) >=
478 NXGE_MAX_RDC_GRPS)) {
speera3c5bd62007-01-30 11:29:19 -0800479 bad_config = B_TRUE;
480 break;
481 }
482 num_grps += custom_num_grp[port];
483 if (num_grps > NXGE_MAX_RDC_GRPS) {
484 bad_config = B_TRUE;
485 break;
486 }
487 grp_bitmap[port] = 0;
488 for (bits = 0;
misaki52ccf842008-06-20 15:53:36 -0700489 bits < custom_num_grp[port];
490 bits++) {
speera3c5bd62007-01-30 11:29:19 -0800491 grp_bitmap[port] |=
misaki52ccf842008-06-20 15:53:36 -0700492 (1 << (bits + custom_start_grp[port]));
speera3c5bd62007-01-30 11:29:19 -0800493 }
494
495 }
496
497 if (bad_config == B_FALSE) {
498 /* check for overlap */
499 for (port = 0; port < num_ports - 1; port++) {
500 for (j = port + 1; j < num_ports; j++) {
501 if (grp_bitmap[port] &
misaki52ccf842008-06-20 15:53:36 -0700502 grp_bitmap[j]) {
speera3c5bd62007-01-30 11:29:19 -0800503 bad_config = B_TRUE;
504 break;
505 }
506 }
507 if (bad_config == B_TRUE)
508 break;
509 }
510 }
511 if (bad_config == B_TRUE) {
512 /* use default config */
girish44961712006-11-22 11:47:19 -0800513 for (port = 0; port < num_ports; port++) {
514 custom_num_grp[port] =
misaki52ccf842008-06-20 15:53:36 -0700515 (num_ports == 4) ?
516 p4_rx_fair[port] : p2_rx_fair[port];
girish44961712006-11-22 11:47:19 -0800517 custom_start_grp[port] = start_grp;
518 start_grp += custom_num_grp[port];
519 }
speera3c5bd62007-01-30 11:29:19 -0800520 }
521 break;
522
523 default:
524 /* use default config */
525 cfg_prop = "fair";
526 for (port = 0; port < num_ports; port++) {
527 custom_num_grp[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700528 p4_rx_fair[port] : p2_rx_fair[port];
speera3c5bd62007-01-30 11:29:19 -0800529 custom_start_grp[port] = start_grp;
530 start_grp += custom_num_grp[port];
531 }
532 break;
girish44961712006-11-22 11:47:19 -0800533 }
534
speera3c5bd62007-01-30 11:29:19 -0800535 /* Now Update the rx properties */
girish44961712006-11-22 11:47:19 -0800536 for (port = 0; port < num_ports; port++) {
537 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700538 "rxdma-grp-cfg", cfg_prop);
girish44961712006-11-22 11:47:19 -0800539 if (ddi_status != DDI_PROP_SUCCESS) {
540 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700541 " property %s not updating",
542 cfg_prop));
girish44961712006-11-22 11:47:19 -0800543 status |= NXGE_DDI_FAILED;
544 }
545 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700546 num_prop, custom_num_grp[port]);
girish44961712006-11-22 11:47:19 -0800547
548 if (ddi_status != DDI_PROP_SUCCESS) {
549 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700550 " property %s not updating",
551 num_prop));
girish44961712006-11-22 11:47:19 -0800552 status |= NXGE_DDI_FAILED;
553 }
554 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700555 start_prop, custom_start_grp[port]);
girish44961712006-11-22 11:47:19 -0800556
557 if (ddi_status != DDI_PROP_SUCCESS) {
558 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700559 " property %s not updating",
560 start_prop));
girish44961712006-11-22 11:47:19 -0800561 status |= NXGE_DDI_FAILED;
562 }
563 }
564 if (status & NXGE_DDI_FAILED)
565 status |= NXGE_ERROR;
566
567 return (status);
girish44961712006-11-22 11:47:19 -0800568}
569
girish44961712006-11-22 11:47:19 -0800570static nxge_status_t
571nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token,
speera3c5bd62007-01-30 11:29:19 -0800572 dev_info_t *s_dip[])
girish44961712006-11-22 11:47:19 -0800573{
574 nxge_status_t status = NXGE_OK;
575 int ddi_status;
576 int num_ports = nxgep->nports;
577 int port, bits, j;
578 uint8_t start_rdc = 0, num_rdc = 0;
579 p_nxge_param_t param_arr;
580 uint32_t rdc_bitmap[MAX_SIBLINGS];
581 int custom_start_rdc[MAX_SIBLINGS];
582 int custom_num_rdc[MAX_SIBLINGS];
583 uint8_t bad_config = B_FALSE;
584 int *prop_val;
585 uint_t prop_len;
586 char *start_rdc_prop, *num_rdc_prop, *cfg_prop;
587
588 start_rdc = 0;
589 param_arr = nxgep->param_arr;
girish44961712006-11-22 11:47:19 -0800590 start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name;
591 num_rdc_prop = param_arr[param_rxdma_channels].fcode_name;
592
593 switch (token) {
speera3c5bd62007-01-30 11:29:19 -0800594 case FAIR:
595 cfg_prop = "fair";
596 for (port = 0; port < num_ports; port++) {
597 custom_num_rdc[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700598 p4_rx_fair[port] : p2_rx_fair[port];
speera3c5bd62007-01-30 11:29:19 -0800599 custom_start_rdc[port] = start_rdc;
600 start_rdc += custom_num_rdc[port];
601 }
girish44961712006-11-22 11:47:19 -0800602 break;
603
speera3c5bd62007-01-30 11:29:19 -0800604 case EQUAL:
605 cfg_prop = "equal";
606 for (port = 0; port < num_ports; port++) {
607 custom_num_rdc[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700608 p4_rx_equal[port] :
609 p2_rx_equal[port];
speera3c5bd62007-01-30 11:29:19 -0800610 custom_start_rdc[port] = start_rdc;
611 start_rdc += custom_num_rdc[port];
612 }
613 break;
girish44961712006-11-22 11:47:19 -0800614
speera3c5bd62007-01-30 11:29:19 -0800615 case CUSTOM:
616 cfg_prop = "custom";
617 /* See if it is good config */
618 num_rdc = 0;
619 for (port = 0; port < num_ports; port++) {
620 ddi_status = ddi_prop_lookup_int_array(
misaki52ccf842008-06-20 15:53:36 -0700621 DDI_DEV_T_ANY,
622 s_dip[port], 0,
623 start_rdc_prop,
624 &prop_val,
625 &prop_len);
speera3c5bd62007-01-30 11:29:19 -0800626 if (ddi_status == DDI_SUCCESS)
627 custom_start_rdc[port] = *prop_val;
628 else {
girish44961712006-11-22 11:47:19 -0800629 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700630 " %s custom start port %d"
631 " read failed ",
632 " rxdma-cfg", port));
speera3c5bd62007-01-30 11:29:19 -0800633 bad_config = B_TRUE;
634 status |= NXGE_DDI_FAILED;
girish44961712006-11-22 11:47:19 -0800635 }
speera3c5bd62007-01-30 11:29:19 -0800636 if ((custom_start_rdc[port] == -1) ||
misaki52ccf842008-06-20 15:53:36 -0700637 (custom_start_rdc[port] >=
638 NXGE_MAX_RDCS)) {
speera3c5bd62007-01-30 11:29:19 -0800639 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700640 " %s custom start %d"
641 " out of range %x ",
642 " rxdma-cfg",
643 port,
644 custom_start_rdc[port]));
speera3c5bd62007-01-30 11:29:19 -0800645 bad_config = B_TRUE;
646 break;
647 }
648 ddi_status = ddi_prop_lookup_int_array(
misaki52ccf842008-06-20 15:53:36 -0700649 DDI_DEV_T_ANY,
650 s_dip[port],
651 0,
652 num_rdc_prop,
653 &prop_val,
654 &prop_len);
girish44961712006-11-22 11:47:19 -0800655
speera3c5bd62007-01-30 11:29:19 -0800656 if (ddi_status == DDI_SUCCESS)
657 custom_num_rdc[port] = *prop_val;
658 else {
659 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700660 " %s custom num port %d"
661 " read failed ",
662 "rxdma-cfg", port));
speera3c5bd62007-01-30 11:29:19 -0800663 bad_config = B_TRUE;
664 status |= NXGE_DDI_FAILED;
665 }
666
667 if ((custom_num_rdc[port] == -1) ||
misaki52ccf842008-06-20 15:53:36 -0700668 (custom_num_rdc[port] >
669 NXGE_MAX_RDCS) ||
670 ((custom_num_rdc[port] +
671 custom_start_rdc[port]) >
672 NXGE_MAX_RDCS)) {
speera3c5bd62007-01-30 11:29:19 -0800673 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700674 " %s custom num %d"
675 " out of range %x ",
676 " rxdma-cfg",
677 port, custom_num_rdc[port]));
speera3c5bd62007-01-30 11:29:19 -0800678 bad_config = B_TRUE;
679 break;
680 }
681 num_rdc += custom_num_rdc[port];
682 if (num_rdc > NXGE_MAX_RDCS) {
683 bad_config = B_TRUE;
684 break;
685 }
686 rdc_bitmap[port] = 0;
687 for (bits = 0;
misaki52ccf842008-06-20 15:53:36 -0700688 bits < custom_num_rdc[port]; bits++) {
speera3c5bd62007-01-30 11:29:19 -0800689 rdc_bitmap[port] |=
misaki52ccf842008-06-20 15:53:36 -0700690 (1 << (bits + custom_start_rdc[port]));
speera3c5bd62007-01-30 11:29:19 -0800691 }
692 }
693
694 if (bad_config == B_FALSE) {
695 /* check for overlap */
696 for (port = 0; port < num_ports - 1; port++) {
697 for (j = port + 1; j < num_ports; j++) {
698 if (rdc_bitmap[port] &
misaki52ccf842008-06-20 15:53:36 -0700699 rdc_bitmap[j]) {
speera3c5bd62007-01-30 11:29:19 -0800700 NXGE_DEBUG_MSG((nxgep,
misaki52ccf842008-06-20 15:53:36 -0700701 CFG_CTL,
702 " rxdma-cfg"
703 " property custom"
704 " bit overlap"
705 " %d %d ",
706 port, j));
speera3c5bd62007-01-30 11:29:19 -0800707 bad_config = B_TRUE;
708 break;
709 }
710 }
711 if (bad_config == B_TRUE)
712 break;
713 }
714 }
715 if (bad_config == B_TRUE) {
716 /* use default config */
717 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700718 " rxdma-cfg property:"
719 " bad custom config:"
720 " use default"));
girish44961712006-11-22 11:47:19 -0800721 for (port = 0; port < num_ports; port++) {
speera3c5bd62007-01-30 11:29:19 -0800722 custom_num_rdc[port] =
misaki52ccf842008-06-20 15:53:36 -0700723 (num_ports == 4) ?
724 p4_rx_fair[port] :
725 p2_rx_fair[port];
girish44961712006-11-22 11:47:19 -0800726 custom_start_rdc[port] = start_rdc;
727 start_rdc += custom_num_rdc[port];
728 }
speera3c5bd62007-01-30 11:29:19 -0800729 }
730 break;
731
732 default:
733 /* use default config */
734 cfg_prop = "fair";
735 for (port = 0; port < num_ports; port++) {
736 custom_num_rdc[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700737 p4_rx_fair[port] : p2_rx_fair[port];
speera3c5bd62007-01-30 11:29:19 -0800738 custom_start_rdc[port] = start_rdc;
739 start_rdc += custom_num_rdc[port];
740 }
741 break;
girish44961712006-11-22 11:47:19 -0800742 }
743
speera3c5bd62007-01-30 11:29:19 -0800744 /* Now Update the rx properties */
girish44961712006-11-22 11:47:19 -0800745 for (port = 0; port < num_ports; port++) {
746 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700747 " update property rxdma-cfg with %s ", cfg_prop));
girish44961712006-11-22 11:47:19 -0800748 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700749 "rxdma-cfg", cfg_prop);
girish44961712006-11-22 11:47:19 -0800750 if (ddi_status != DDI_PROP_SUCCESS) {
751 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700752 " property rxdma-cfg is not updating to %s",
753 cfg_prop));
girish44961712006-11-22 11:47:19 -0800754 status |= NXGE_DDI_FAILED;
755 }
girish44961712006-11-22 11:47:19 -0800756 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
misaki52ccf842008-06-20 15:53:36 -0700757 num_rdc_prop, custom_num_rdc[port]));
girish44961712006-11-22 11:47:19 -0800758
759 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700760 num_rdc_prop, custom_num_rdc[port]);
girish44961712006-11-22 11:47:19 -0800761
762 if (ddi_status != DDI_PROP_SUCCESS) {
763 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700764 " property %s not updating with %d",
765 num_rdc_prop, custom_num_rdc[port]));
girish44961712006-11-22 11:47:19 -0800766 status |= NXGE_DDI_FAILED;
767 }
girish44961712006-11-22 11:47:19 -0800768 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
misaki52ccf842008-06-20 15:53:36 -0700769 start_rdc_prop, custom_start_rdc[port]));
girish44961712006-11-22 11:47:19 -0800770 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700771 start_rdc_prop, custom_start_rdc[port]);
girish44961712006-11-22 11:47:19 -0800772
773 if (ddi_status != DDI_PROP_SUCCESS) {
774 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700775 " property %s not updating with %d ",
776 start_rdc_prop, custom_start_rdc[port]));
girish44961712006-11-22 11:47:19 -0800777 status |= NXGE_DDI_FAILED;
778 }
779 }
780 if (status & NXGE_DDI_FAILED)
781 status |= NXGE_ERROR;
782 return (status);
girish44961712006-11-22 11:47:19 -0800783}
784
785static nxge_status_t
786nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token,
speera3c5bd62007-01-30 11:29:19 -0800787 dev_info_t *s_dip[])
girish44961712006-11-22 11:47:19 -0800788{
789 nxge_status_t status = NXGE_OK;
790 int ddi_status = DDI_SUCCESS;
791 int num_ports = nxgep->nports;
792 int port, bits, j;
Eric Chengda14ceb2008-12-04 18:16:10 -0800793 uint8_t start_tdc, num_tdc = 0;
girish44961712006-11-22 11:47:19 -0800794 p_nxge_param_t param_arr;
795 uint32_t tdc_bitmap[MAX_SIBLINGS];
796 int custom_start_tdc[MAX_SIBLINGS];
797 int custom_num_tdc[MAX_SIBLINGS];
798 uint8_t bad_config = B_FALSE;
799 int *prop_val;
800 uint_t prop_len;
801 char *start_tdc_prop, *num_tdc_prop, *cfg_prop;
802
803 start_tdc = 0;
804 param_arr = nxgep->param_arr;
girish44961712006-11-22 11:47:19 -0800805 start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name;
806 num_tdc_prop = param_arr[param_txdma_channels].fcode_name;
807
808 switch (token) {
speera3c5bd62007-01-30 11:29:19 -0800809 case FAIR:
810 cfg_prop = "fair";
811 for (port = 0; port < num_ports; port++) {
812 custom_num_tdc[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700813 p4_tx_fair[port] : p2_tx_fair[port];
speera3c5bd62007-01-30 11:29:19 -0800814 custom_start_tdc[port] = start_tdc;
815 start_tdc += custom_num_tdc[port];
816 }
girish44961712006-11-22 11:47:19 -0800817 break;
818
speera3c5bd62007-01-30 11:29:19 -0800819 case EQUAL:
820 cfg_prop = "equal";
821 for (port = 0; port < num_ports; port++) {
822 custom_num_tdc[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700823 p4_tx_equal[port] : p2_tx_equal[port];
speera3c5bd62007-01-30 11:29:19 -0800824 custom_start_tdc[port] = start_tdc;
825 start_tdc += custom_num_tdc[port];
826 }
827 break;
girish44961712006-11-22 11:47:19 -0800828
speera3c5bd62007-01-30 11:29:19 -0800829 case CUSTOM:
830 cfg_prop = "custom";
831 /* See if it is good config */
832 num_tdc = 0;
833 for (port = 0; port < num_ports; port++) {
834 ddi_status = ddi_prop_lookup_int_array(
misaki52ccf842008-06-20 15:53:36 -0700835 DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop,
836 &prop_val, &prop_len);
speera3c5bd62007-01-30 11:29:19 -0800837 if (ddi_status == DDI_SUCCESS)
838 custom_start_tdc[port] = *prop_val;
839 else {
girish44961712006-11-22 11:47:19 -0800840 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700841 " %s custom start port %d"
842 " read failed ", " txdma-cfg", port));
speera3c5bd62007-01-30 11:29:19 -0800843 bad_config = B_TRUE;
844 status |= NXGE_DDI_FAILED;
girish44961712006-11-22 11:47:19 -0800845 }
girish44961712006-11-22 11:47:19 -0800846
speera3c5bd62007-01-30 11:29:19 -0800847 if ((custom_start_tdc[port] == -1) ||
misaki52ccf842008-06-20 15:53:36 -0700848 (custom_start_tdc[port] >=
849 NXGE_MAX_RDCS)) {
speera3c5bd62007-01-30 11:29:19 -0800850 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700851 " %s custom start %d"
852 " out of range %x ", " txdma-cfg",
853 port, custom_start_tdc[port]));
speera3c5bd62007-01-30 11:29:19 -0800854 bad_config = B_TRUE;
855 break;
856 }
857
858 ddi_status = ddi_prop_lookup_int_array(
misaki52ccf842008-06-20 15:53:36 -0700859 DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop,
860 &prop_val, &prop_len);
speera3c5bd62007-01-30 11:29:19 -0800861 if (ddi_status == DDI_SUCCESS)
862 custom_num_tdc[port] = *prop_val;
863 else {
864 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700865 " %s custom num port %d"
866 " read failed ", " txdma-cfg", port));
speera3c5bd62007-01-30 11:29:19 -0800867 bad_config = B_TRUE;
868 status |= NXGE_DDI_FAILED;
869 }
870
871 if ((custom_num_tdc[port] == -1) ||
misaki52ccf842008-06-20 15:53:36 -0700872 (custom_num_tdc[port] >
873 NXGE_MAX_TDCS) ||
874 ((custom_num_tdc[port] +
875 custom_start_tdc[port]) >
876 NXGE_MAX_TDCS)) {
speera3c5bd62007-01-30 11:29:19 -0800877 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700878 " %s custom num %d"
879 " out of range %x ", " rxdma-cfg",
880 port, custom_num_tdc[port]));
speera3c5bd62007-01-30 11:29:19 -0800881 bad_config = B_TRUE;
882 break;
883 }
884 num_tdc += custom_num_tdc[port];
885 if (num_tdc > NXGE_MAX_TDCS) {
886 bad_config = B_TRUE;
887 break;
888 }
889 tdc_bitmap[port] = 0;
890 for (bits = 0;
misaki52ccf842008-06-20 15:53:36 -0700891 bits < custom_num_tdc[port]; bits++) {
speera3c5bd62007-01-30 11:29:19 -0800892 tdc_bitmap[port] |=
misaki52ccf842008-06-20 15:53:36 -0700893 (1 <<
894 (bits + custom_start_tdc[port]));
speera3c5bd62007-01-30 11:29:19 -0800895 }
896
897 }
898
899 if (bad_config == B_FALSE) {
900 /* check for overlap */
901 for (port = 0; port < num_ports - 1; port++) {
902 for (j = port + 1; j < num_ports; j++) {
903 if (tdc_bitmap[port] &
misaki52ccf842008-06-20 15:53:36 -0700904 tdc_bitmap[j]) {
speera3c5bd62007-01-30 11:29:19 -0800905 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700906 " rxdma-cfg"
907 " property custom"
908 " bit overlap"
909 " %d %d ",
910 port, j));
speera3c5bd62007-01-30 11:29:19 -0800911 bad_config = B_TRUE;
912 break;
913 }
914 }
915 if (bad_config == B_TRUE)
916 break;
917 }
918 }
919 if (bad_config == B_TRUE) {
920 /* use default config */
921 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700922 " txdma-cfg property:"
923 " bad custom config:" " use default"));
speera3c5bd62007-01-30 11:29:19 -0800924
girish44961712006-11-22 11:47:19 -0800925 for (port = 0; port < num_ports; port++) {
926 custom_num_tdc[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700927 p4_tx_fair[port] : p2_tx_fair[port];
girish44961712006-11-22 11:47:19 -0800928 custom_start_tdc[port] = start_tdc;
929 start_tdc += custom_num_tdc[port];
930 }
speera3c5bd62007-01-30 11:29:19 -0800931 }
932 break;
933
934 default:
935 /* use default config */
936 cfg_prop = "fair";
937 for (port = 0; port < num_ports; port++) {
938 custom_num_tdc[port] = (num_ports == 4) ?
misaki52ccf842008-06-20 15:53:36 -0700939 p4_tx_fair[port] : p2_tx_fair[port];
speera3c5bd62007-01-30 11:29:19 -0800940 custom_start_tdc[port] = start_tdc;
941 start_tdc += custom_num_tdc[port];
942 }
943 break;
girish44961712006-11-22 11:47:19 -0800944 }
945
speera3c5bd62007-01-30 11:29:19 -0800946 /* Now Update the tx properties */
girish44961712006-11-22 11:47:19 -0800947 for (port = 0; port < num_ports; port++) {
948 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700949 " update property txdma-cfg with %s ", cfg_prop));
girish44961712006-11-22 11:47:19 -0800950 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700951 "txdma-cfg", cfg_prop);
girish44961712006-11-22 11:47:19 -0800952 if (ddi_status != DDI_PROP_SUCCESS) {
953 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -0700954 " property txdma-cfg is not updating to %s",
955 cfg_prop));
speera3c5bd62007-01-30 11:29:19 -0800956 status |= NXGE_DDI_FAILED;
957 }
958 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
misaki52ccf842008-06-20 15:53:36 -0700959 num_tdc_prop, custom_num_tdc[port]));
speera3c5bd62007-01-30 11:29:19 -0800960
961 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700962 num_tdc_prop, custom_num_tdc[port]);
speera3c5bd62007-01-30 11:29:19 -0800963
964 if (ddi_status != DDI_PROP_SUCCESS) {
965 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700966 " property %s not updating with %d",
967 num_tdc_prop,
968 custom_num_tdc[port]));
girish44961712006-11-22 11:47:19 -0800969 status |= NXGE_DDI_FAILED;
970 }
971
972 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
misaki52ccf842008-06-20 15:53:36 -0700973 start_tdc_prop, custom_start_tdc[port]));
girish44961712006-11-22 11:47:19 -0800974
975 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
misaki52ccf842008-06-20 15:53:36 -0700976 start_tdc_prop, custom_start_tdc[port]);
girish44961712006-11-22 11:47:19 -0800977 if (ddi_status != DDI_PROP_SUCCESS) {
978 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -0700979 " property %s not updating with %d ",
980 start_tdc_prop, custom_start_tdc[port]));
girish44961712006-11-22 11:47:19 -0800981 status |= NXGE_DDI_FAILED;
982 }
983 }
984 if (status & NXGE_DDI_FAILED)
985 status |= NXGE_ERROR;
986 return (status);
girish44961712006-11-22 11:47:19 -0800987}
988
girish44961712006-11-22 11:47:19 -0800989static nxge_status_t
990nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags,
speera3c5bd62007-01-30 11:29:19 -0800991 config_token_t token, dev_info_t *s_dip[])
girish44961712006-11-22 11:47:19 -0800992{
girish44961712006-11-22 11:47:19 -0800993 nxge_status_t status = NXGE_OK;
994
995 switch (flags) {
speera3c5bd62007-01-30 11:29:19 -0800996 case COMMON_TXDMA_CFG:
997 if (nxge_dma_obp_props_only == 0)
girish44961712006-11-22 11:47:19 -0800998 status = nxge_update_txdma_properties(nxgep,
misaki52ccf842008-06-20 15:53:36 -0700999 token, s_dip);
speera3c5bd62007-01-30 11:29:19 -08001000 break;
1001 case COMMON_RXDMA_CFG:
1002 if (nxge_dma_obp_props_only == 0)
girish44961712006-11-22 11:47:19 -08001003 status = nxge_update_rxdma_properties(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001004 token, s_dip);
girish44961712006-11-22 11:47:19 -08001005
speera3c5bd62007-01-30 11:29:19 -08001006 break;
1007 case COMMON_RXDMA_GRP_CFG:
1008 status = nxge_update_rxdma_grp_properties(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001009 token, s_dip);
speera3c5bd62007-01-30 11:29:19 -08001010 break;
1011 default:
1012 return (NXGE_ERROR);
girish44961712006-11-22 11:47:19 -08001013 }
1014 return (status);
1015}
1016
girish44961712006-11-22 11:47:19 -08001017/*
1018 * verify consistence.
1019 * (May require publishing the properties on all the ports.
1020 *
1021 * What if properties are published on function 0 device only?
1022 *
1023 *
1024 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required )
1025 * What about class configs?
1026 *
1027 * If consistent, update the property on all the siblings.
1028 * set a flag on hardware shared register
1029 * The rest of the siblings will check the flag
1030 * if the flag is set, they will use the updated property
1031 * without doing any validation.
1032 */
1033
girish44961712006-11-22 11:47:19 -08001034nxge_status_t
1035nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop,
speera3c5bd62007-01-30 11:29:19 -08001036 uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[])
girish44961712006-11-22 11:47:19 -08001037{
1038 nxge_status_t status = NXGE_OK;
1039 int ddi_status = DDI_SUCCESS;
1040 int i = 0, found = 0, update_prop = B_TRUE;
speera3c5bd62007-01-30 11:29:19 -08001041 int *cfg_val;
1042 uint_t new_value, cfg_value[MAX_SIBLINGS];
1043 uint_t prop_len;
girish44961712006-11-22 11:47:19 -08001044 uint_t known_cfg_value;
1045
1046 known_cfg_value = (uint_t)known_cfg;
1047
1048 if (override == B_TRUE) {
1049 new_value = known_cfg_value;
1050 for (i = 0; i < nxgep->nports; i++) {
1051 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
misaki52ccf842008-06-20 15:53:36 -07001052 c_dip[i], prop, new_value);
girish44961712006-11-22 11:47:19 -08001053#ifdef NXGE_DEBUG_ERROR
1054 if (ddi_status != DDI_PROP_SUCCESS)
1055 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -07001056 " property %s failed update ", prop));
girish44961712006-11-22 11:47:19 -08001057#endif
1058 }
1059 if (ddi_status != DDI_PROP_SUCCESS)
1060 return (NXGE_ERROR | NXGE_DDI_FAILED);
1061 }
girish44961712006-11-22 11:47:19 -08001062 for (i = 0; i < nxgep->nports; i++) {
1063 cfg_value[i] = known_cfg_value;
1064 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0,
misaki52ccf842008-06-20 15:53:36 -07001065 prop, &cfg_val,
1066 &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001067 cfg_value[i] = *cfg_val;
1068 ddi_prop_free(cfg_val);
1069 found++;
1070 }
1071 }
1072
1073 if (found != i) {
1074 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001075 " property %s not specified on all ports", prop));
girish44961712006-11-22 11:47:19 -08001076 if (found == 0) {
speera3c5bd62007-01-30 11:29:19 -08001077 /* not specified: Use default */
girish44961712006-11-22 11:47:19 -08001078 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001079 " property %s not specified on any port:"
1080 " Using default", prop));
girish44961712006-11-22 11:47:19 -08001081 new_value = known_cfg_value;
1082 } else {
speera3c5bd62007-01-30 11:29:19 -08001083 /* specified on some */
girish44961712006-11-22 11:47:19 -08001084 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001085 " property %s not specified"
1086 " on some ports: Using default", prop));
girish44961712006-11-22 11:47:19 -08001087 /* ? use p0 value instead ? */
1088 new_value = known_cfg_value;
1089 }
1090 } else {
1091 /* check type and consistence */
1092 /* found on all devices */
1093 for (i = 1; i < found; i++) {
speera3c5bd62007-01-30 11:29:19 -08001094 if (cfg_value[i] != cfg_value[i - 1]) {
girish44961712006-11-22 11:47:19 -08001095 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001096 " property %s inconsistent:"
1097 " Using default", prop));
girish44961712006-11-22 11:47:19 -08001098 new_value = known_cfg_value;
1099 break;
speera3c5bd62007-01-30 11:29:19 -08001100 }
1101 /*
1102 * Found on all the ports and consistent. Nothing to
1103 * do.
1104 */
girish44961712006-11-22 11:47:19 -08001105 update_prop = B_FALSE;
1106 }
girish44961712006-11-22 11:47:19 -08001107 }
1108
1109 if (update_prop == B_TRUE) {
1110 for (i = 0; i < nxgep->nports; i++) {
1111 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
misaki52ccf842008-06-20 15:53:36 -07001112 c_dip[i], prop, new_value);
girish44961712006-11-22 11:47:19 -08001113#ifdef NXGE_DEBUG_ERROR
1114 if (ddi_status != DDI_SUCCESS)
1115 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -07001116 " property %s not updating with %d"
1117 " Using default",
1118 prop, new_value));
girish44961712006-11-22 11:47:19 -08001119#endif
1120 if (ddi_status != DDI_PROP_SUCCESS)
1121 status |= NXGE_DDI_FAILED;
1122 }
1123 }
1124 if (status & NXGE_DDI_FAILED)
1125 status |= NXGE_ERROR;
1126
1127 return (status);
1128}
1129
1130static uint64_t
speera3c5bd62007-01-30 11:29:19 -08001131nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg)
girish44961712006-11-22 11:47:19 -08001132{
speera3c5bd62007-01-30 11:29:19 -08001133 int start_prop;
girish44961712006-11-22 11:47:19 -08001134 uint64_t cfg_value;
girish44961712006-11-22 11:47:19 -08001135 p_nxge_param_t param_arr;
girish44961712006-11-22 11:47:19 -08001136
speera3c5bd62007-01-30 11:29:19 -08001137 param_arr = nxgep->param_arr;
girish44961712006-11-22 11:47:19 -08001138 cfg_value = param_arr[class_prop].value;
1139 start_prop = param_h1_init_value;
1140
1141 /* update the properties per quick config */
girish44961712006-11-22 11:47:19 -08001142 switch (rx_quick_cfg) {
speera3c5bd62007-01-30 11:29:19 -08001143 case CFG_L3_WEB:
1144 case CFG_L3_DISTRIBUTE:
1145 cfg_value = nxge_classify_get_cfg_value(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001146 rx_quick_cfg, class_prop - start_prop);
speera3c5bd62007-01-30 11:29:19 -08001147 break;
1148 default:
1149 cfg_value = param_arr[class_prop].value;
1150 break;
girish44961712006-11-22 11:47:19 -08001151 }
girish44961712006-11-22 11:47:19 -08001152 return (cfg_value);
girish44961712006-11-22 11:47:19 -08001153}
1154
girish44961712006-11-22 11:47:19 -08001155static nxge_status_t
1156nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[])
1157{
girish44961712006-11-22 11:47:19 -08001158 nxge_status_t status = NXGE_OK;
speera3c5bd62007-01-30 11:29:19 -08001159 int rx_quick_cfg, class_prop, start_prop, end_prop;
girish44961712006-11-22 11:47:19 -08001160 char *prop_name;
1161 int override = B_TRUE;
1162 uint64_t cfg_value;
1163 p_nxge_param_t param_arr;
speera3c5bd62007-01-30 11:29:19 -08001164
girish44961712006-11-22 11:47:19 -08001165 param_arr = nxgep->param_arr;
1166 rx_quick_cfg = param_arr[param_rx_quick_cfg].value;
1167 start_prop = param_h1_init_value;
1168 end_prop = param_class_opt_ipv6_sctp;
girish44961712006-11-22 11:47:19 -08001169
speera3c5bd62007-01-30 11:29:19 -08001170 /* update the properties per quick config */
girish44961712006-11-22 11:47:19 -08001171 if (rx_quick_cfg == CFG_NOT_SPECIFIED)
1172 override = B_FALSE;
speera3c5bd62007-01-30 11:29:19 -08001173
1174 /*
1175 * these parameter affect the classification outcome.
1176 * these parameters are used to configure the Flow key and
1177 * the TCAM key for each of the IP classes.
speer58324df2007-02-22 15:55:32 -08001178 * Included here are also the H1 and H2 initial values
speera3c5bd62007-01-30 11:29:19 -08001179 * which affect the distribution as well as final hash value
1180 * (hence the offset into RDC table and FCRAM bucket location)
1181 *
1182 */
1183 for (class_prop = start_prop; class_prop <= end_prop; class_prop++) {
girish44961712006-11-22 11:47:19 -08001184 prop_name = param_arr[class_prop].fcode_name;
1185 cfg_value = nxge_class_get_known_cfg(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001186 class_prop, rx_quick_cfg);
speera3c5bd62007-01-30 11:29:19 -08001187 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
misaki52ccf842008-06-20 15:53:36 -07001188 cfg_value, override, c_dip);
girish44961712006-11-22 11:47:19 -08001189 }
1190
speera3c5bd62007-01-30 11:29:19 -08001191 /*
1192 * these properties do not affect the actual classification outcome.
1193 * used to enable/disable or tune the fflp hardware
1194 *
1195 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable
1196 *
1197 */
girish44961712006-11-22 11:47:19 -08001198 override = B_FALSE;
1199 for (class_prop = param_fcram_access_ratio;
misaki52ccf842008-06-20 15:53:36 -07001200 class_prop <= param_llc_snap_enable; class_prop++) {
girish44961712006-11-22 11:47:19 -08001201 prop_name = param_arr[class_prop].fcode_name;
1202 cfg_value = param_arr[class_prop].value;
1203 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
misaki52ccf842008-06-20 15:53:36 -07001204 cfg_value, override, c_dip);
girish44961712006-11-22 11:47:19 -08001205 }
speera3c5bd62007-01-30 11:29:19 -08001206
girish44961712006-11-22 11:47:19 -08001207 return (status);
girish44961712006-11-22 11:47:19 -08001208}
1209
girish44961712006-11-22 11:47:19 -08001210nxge_status_t
1211nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag)
1212{
girish44961712006-11-22 11:47:19 -08001213 nxge_status_t status = NXGE_OK;
1214 int i = 0, found = 0;
1215 int num_siblings;
speera3c5bd62007-01-30 11:29:19 -08001216 dev_info_t *c_dip[MAX_SIBLINGS + 1];
girish44961712006-11-22 11:47:19 -08001217 char *prop_val[MAX_SIBLINGS];
1218 config_token_t c_token[MAX_SIBLINGS];
1219 char *prop;
1220
speera3c5bd62007-01-30 11:29:19 -08001221 if (nxge_dma_obp_props_only)
girish44961712006-11-22 11:47:19 -08001222 return (NXGE_OK);
girish44961712006-11-22 11:47:19 -08001223
1224 num_siblings = 0;
1225 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip);
1226 while (c_dip[num_siblings]) {
1227 c_dip[num_siblings + 1] =
misaki52ccf842008-06-20 15:53:36 -07001228 ddi_get_next_sibling(c_dip[num_siblings]);
girish44961712006-11-22 11:47:19 -08001229 num_siblings++;
1230 }
1231
girish44961712006-11-22 11:47:19 -08001232 switch (flag) {
speera3c5bd62007-01-30 11:29:19 -08001233 case COMMON_TXDMA_CFG:
1234 prop = "txdma-cfg";
1235 break;
1236 case COMMON_RXDMA_CFG:
1237 prop = "rxdma-cfg";
1238 break;
1239 case COMMON_RXDMA_GRP_CFG:
1240 prop = "rxdma-grp-cfg";
1241 break;
1242 case COMMON_CLASS_CFG:
1243 status = nxge_cfg_verify_set_classify(nxgep, c_dip);
1244 return (status);
1245 default:
1246 return (NXGE_ERROR);
girish44961712006-11-22 11:47:19 -08001247 }
1248
girish44961712006-11-22 11:47:19 -08001249 i = 0;
1250 while (i < num_siblings) {
speera3c5bd62007-01-30 11:29:19 -08001251 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop,
misaki52ccf842008-06-20 15:53:36 -07001252 (char **)&prop_val[i]) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001253 c_token[i] = nxge_get_config_token(prop_val[i]);
1254 ddi_prop_free(prop_val[i]);
1255 found++;
1256 } else
1257 c_token[i] = CONFIG_TOKEN_NONE;
1258 i++;
1259 }
1260
girish44961712006-11-22 11:47:19 -08001261 if (found != i) {
1262 if (found == 0) {
speera3c5bd62007-01-30 11:29:19 -08001263 /* not specified: Use default */
girish44961712006-11-22 11:47:19 -08001264 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001265 " property %s not specified on any port:"
1266 " Using default", prop));
girish44961712006-11-22 11:47:19 -08001267
1268 status = nxge_update_cfg_properties(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001269 flag, FAIR, c_dip);
girish44961712006-11-22 11:47:19 -08001270 return (status);
1271 } else {
1272 /*
speera3c5bd62007-01-30 11:29:19 -08001273 * if the convention is to use function 0 device then
1274 * populate the other devices with this configuration.
girish44961712006-11-22 11:47:19 -08001275 *
1276 * The other alternative is to use the default config.
1277 */
speera3c5bd62007-01-30 11:29:19 -08001278 /* not specified: Use default */
girish44961712006-11-22 11:47:19 -08001279 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001280 " property %s not specified on some ports:"
1281 " Using default", prop));
girish44961712006-11-22 11:47:19 -08001282 status = nxge_update_cfg_properties(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001283 flag, FAIR, c_dip);
girish44961712006-11-22 11:47:19 -08001284 return (status);
1285 }
1286 }
speera3c5bd62007-01-30 11:29:19 -08001287
1288 /* check type and consistence */
1289 /* found on all devices */
girish44961712006-11-22 11:47:19 -08001290 for (i = 1; i < found; i++) {
speera3c5bd62007-01-30 11:29:19 -08001291 if (c_token[i] != c_token[i - 1]) {
girish44961712006-11-22 11:47:19 -08001292 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001293 " property %s inconsistent:"
1294 " Using default", prop));
girish44961712006-11-22 11:47:19 -08001295 status = nxge_update_cfg_properties(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001296 flag, FAIR, c_dip);
girish44961712006-11-22 11:47:19 -08001297 return (status);
1298 }
1299 }
girish44961712006-11-22 11:47:19 -08001300
speera3c5bd62007-01-30 11:29:19 -08001301 /*
1302 * Found on all the ports check if it is custom configuration. if
1303 * custom, then verify consistence
1304 *
1305 * finally create soft properties
1306 */
1307 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip);
girish44961712006-11-22 11:47:19 -08001308 return (status);
1309}
1310
girish44961712006-11-22 11:47:19 -08001311nxge_status_t
1312nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)
1313{
1314 nxge_status_t status = NXGE_OK;
1315 int ddi_status = DDI_SUCCESS;
1316 char *prop_val;
1317 char *rx_prop;
1318 char *prop;
1319 uint32_t cfg_value = CFG_NOT_SPECIFIED;
1320 p_nxge_param_t param_arr;
girish44961712006-11-22 11:47:19 -08001321
speera3c5bd62007-01-30 11:29:19 -08001322 param_arr = nxgep->param_arr;
girish44961712006-11-22 11:47:19 -08001323 rx_prop = param_arr[param_rx_quick_cfg].fcode_name;
1324
1325 prop = "rx-quick-cfg";
girish44961712006-11-22 11:47:19 -08001326
speera3c5bd62007-01-30 11:29:19 -08001327 /*
1328 * good value are
1329 *
1330 * "web-server" "generic-server" "l3-classify" "flow-classify"
1331 */
girish44961712006-11-22 11:47:19 -08001332 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
misaki52ccf842008-06-20 15:53:36 -07001333 prop, (char **)&prop_val) != DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001334 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
misaki52ccf842008-06-20 15:53:36 -07001335 " property %s not specified: using default ", prop));
girish44961712006-11-22 11:47:19 -08001336 cfg_value = CFG_NOT_SPECIFIED;
1337 } else {
1338 cfg_value = CFG_L3_DISTRIBUTE;
1339 if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) {
1340 cfg_value = CFG_L3_WEB;
1341 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001342 " %s: web server ", prop));
girish44961712006-11-22 11:47:19 -08001343 }
1344 if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) {
1345 cfg_value = CFG_L3_DISTRIBUTE;
1346 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
misaki52ccf842008-06-20 15:53:36 -07001347 " %s: distribute ", prop));
girish44961712006-11-22 11:47:19 -08001348 }
1349 /* more */
girish44961712006-11-22 11:47:19 -08001350 ddi_prop_free(prop_val);
1351 }
1352
1353 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
misaki52ccf842008-06-20 15:53:36 -07001354 rx_prop, cfg_value);
girish44961712006-11-22 11:47:19 -08001355 if (ddi_status != DDI_PROP_SUCCESS)
1356 status |= NXGE_DDI_FAILED;
girish44961712006-11-22 11:47:19 -08001357
speera3c5bd62007-01-30 11:29:19 -08001358 /* now handle specified cases: */
girish44961712006-11-22 11:47:19 -08001359 if (status & NXGE_DDI_FAILED)
1360 status |= NXGE_ERROR;
girish44961712006-11-22 11:47:19 -08001361 return (status);
1362}
1363
yc14809700161852008-06-09 20:15:04 -07001364/*
1365 * Device properties adv-autoneg-cap etc are defined by FWARC
1366 * http://sac.sfbay/FWARC/2002/345/20020610_asif.haswarey
1367 */
girish44961712006-11-22 11:47:19 -08001368static void
1369nxge_use_cfg_link_cfg(p_nxge_t nxgep)
1370{
1371 int *prop_val;
1372 uint_t prop_len;
1373 dev_info_t *dip;
1374 int speed;
1375 int duplex;
1376 int adv_autoneg_cap;
1377 int adv_10gfdx_cap;
1378 int adv_10ghdx_cap;
1379 int adv_1000fdx_cap;
1380 int adv_1000hdx_cap;
1381 int adv_100fdx_cap;
1382 int adv_100hdx_cap;
1383 int adv_10fdx_cap;
1384 int adv_10hdx_cap;
1385 int status = DDI_SUCCESS;
1386
1387 dip = nxgep->dip;
speera3c5bd62007-01-30 11:29:19 -08001388
1389 /*
1390 * first find out the card type and the supported link speeds and
1391 * features
1392 */
1393 /* add code for card type */
girish44961712006-11-22 11:47:19 -08001394 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap",
misaki52ccf842008-06-20 15:53:36 -07001395 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001396 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001397 return;
girish44961712006-11-22 11:47:19 -08001398 }
speera3c5bd62007-01-30 11:29:19 -08001399
girish44961712006-11-22 11:47:19 -08001400 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap",
misaki52ccf842008-06-20 15:53:36 -07001401 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001402 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001403 return;
girish44961712006-11-22 11:47:19 -08001404 }
speera3c5bd62007-01-30 11:29:19 -08001405
girish44961712006-11-22 11:47:19 -08001406 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap",
misaki52ccf842008-06-20 15:53:36 -07001407 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001408 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001409 return;
girish44961712006-11-22 11:47:19 -08001410 }
speera3c5bd62007-01-30 11:29:19 -08001411
girish44961712006-11-22 11:47:19 -08001412 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap",
misaki52ccf842008-06-20 15:53:36 -07001413 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001414 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001415 return;
girish44961712006-11-22 11:47:19 -08001416 }
speera3c5bd62007-01-30 11:29:19 -08001417
girish44961712006-11-22 11:47:19 -08001418 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap",
misaki52ccf842008-06-20 15:53:36 -07001419 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001420 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001421 return;
girish44961712006-11-22 11:47:19 -08001422 }
speera3c5bd62007-01-30 11:29:19 -08001423
girish44961712006-11-22 11:47:19 -08001424 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap",
misaki52ccf842008-06-20 15:53:36 -07001425 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001426 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001427 return;
girish44961712006-11-22 11:47:19 -08001428 }
speera3c5bd62007-01-30 11:29:19 -08001429
girish44961712006-11-22 11:47:19 -08001430 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap",
misaki52ccf842008-06-20 15:53:36 -07001431 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001432 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001433 return;
girish44961712006-11-22 11:47:19 -08001434 }
speera3c5bd62007-01-30 11:29:19 -08001435
girish44961712006-11-22 11:47:19 -08001436 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap",
misaki52ccf842008-06-20 15:53:36 -07001437 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001438 ddi_prop_free(prop_val);
speera3c5bd62007-01-30 11:29:19 -08001439 return;
girish44961712006-11-22 11:47:19 -08001440 }
1441
1442 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed",
misaki52ccf842008-06-20 15:53:36 -07001443 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001444 if (strncmp("10000", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001445 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001446 speed = 10000;
1447 } else if (strncmp("1000", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001448 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001449 speed = 1000;
1450 } else if (strncmp("100", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001451 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001452 speed = 100;
1453 } else if (strncmp("10", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001454 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001455 speed = 10;
1456 } else if (strncmp("auto", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001457 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001458 speed = 0;
1459 } else {
1460 NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
misaki52ccf842008-06-20 15:53:36 -07001461 "speed property is invalid reverting to auto"));
girish44961712006-11-22 11:47:19 -08001462 speed = 0;
1463 }
1464 ddi_prop_free(prop_val);
1465 } else
1466 speed = 0;
1467
1468 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex",
misaki52ccf842008-06-20 15:53:36 -07001469 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
girish44961712006-11-22 11:47:19 -08001470 if (strncmp("full", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001471 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001472 duplex = 2;
1473 } else if (strncmp("half", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001474 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001475 duplex = 1;
1476 } else if (strncmp("auto", (caddr_t)prop_val,
misaki52ccf842008-06-20 15:53:36 -07001477 (size_t)prop_len) == 0) {
girish44961712006-11-22 11:47:19 -08001478 duplex = 0;
1479 } else {
1480 NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
misaki52ccf842008-06-20 15:53:36 -07001481 "duplex property is invalid"
1482 " reverting to auto"));
girish44961712006-11-22 11:47:19 -08001483 duplex = 0;
1484 }
1485 ddi_prop_free(prop_val);
1486 } else
1487 duplex = 0;
1488
yc14809700161852008-06-09 20:15:04 -07001489 /* speed == 0 or duplex == 0 means auto negotiation. */
girish44961712006-11-22 11:47:19 -08001490 adv_autoneg_cap = (speed == 0) || (duplex == 0);
1491 if (adv_autoneg_cap == 0) {
1492 adv_10gfdx_cap = ((speed == 10000) && (duplex == 2));
1493 adv_10ghdx_cap = adv_10gfdx_cap;
1494 adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1));
1495 adv_1000fdx_cap = adv_10ghdx_cap;
1496 adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2));
1497 adv_1000hdx_cap = adv_1000fdx_cap;
1498 adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1));
1499 adv_100fdx_cap = adv_1000hdx_cap;
1500 adv_100fdx_cap |= ((speed == 100) && (duplex == 2));
1501 adv_100hdx_cap = adv_100fdx_cap;
1502 adv_100hdx_cap |= ((speed == 100) && (duplex == 1));
1503 adv_10fdx_cap = adv_100hdx_cap;
1504 adv_10fdx_cap |= ((speed == 10) && (duplex == 2));
1505 adv_10hdx_cap = adv_10fdx_cap;
1506 adv_10hdx_cap |= ((speed == 10) && (duplex == 1));
1507 } else if (speed == 0) {
1508 adv_10gfdx_cap = (duplex == 2);
1509 adv_10ghdx_cap = (duplex == 1);
1510 adv_1000fdx_cap = (duplex == 2);
1511 adv_1000hdx_cap = (duplex == 1);
1512 adv_100fdx_cap = (duplex == 2);
1513 adv_100hdx_cap = (duplex == 1);
1514 adv_10fdx_cap = (duplex == 2);
1515 adv_10hdx_cap = (duplex == 1);
1516 }
1517 if (duplex == 0) {
1518 adv_10gfdx_cap = (speed == 0);
1519 adv_10gfdx_cap |= (speed == 10000);
1520 adv_10ghdx_cap = adv_10gfdx_cap;
1521 adv_10ghdx_cap |= (speed == 10000);
1522 adv_1000fdx_cap = adv_10ghdx_cap;
1523 adv_1000fdx_cap |= (speed == 1000);
1524 adv_1000hdx_cap = adv_1000fdx_cap;
1525 adv_1000hdx_cap |= (speed == 1000);
1526 adv_100fdx_cap = adv_1000hdx_cap;
1527 adv_100fdx_cap |= (speed == 100);
1528 adv_100hdx_cap = adv_100fdx_cap;
1529 adv_100hdx_cap |= (speed == 100);
1530 adv_10fdx_cap = adv_100hdx_cap;
1531 adv_10fdx_cap |= (speed == 10);
1532 adv_10hdx_cap = adv_10fdx_cap;
1533 adv_10hdx_cap |= (speed == 10);
1534 }
girish44961712006-11-22 11:47:19 -08001535 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001536 "adv-autoneg-cap", &adv_autoneg_cap, 1);
girish44961712006-11-22 11:47:19 -08001537 if (status)
speera3c5bd62007-01-30 11:29:19 -08001538 return;
girish44961712006-11-22 11:47:19 -08001539
1540 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001541 "adv-10gfdx-cap", &adv_10gfdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001542 if (status)
1543 goto nxge_map_myargs_to_gmii_fail1;
1544
1545 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001546 "adv-10ghdx-cap", &adv_10ghdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001547 if (status)
1548 goto nxge_map_myargs_to_gmii_fail2;
1549
1550 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001551 "adv-1000fdx-cap", &adv_1000fdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001552 if (status)
1553 goto nxge_map_myargs_to_gmii_fail3;
1554
1555 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001556 "adv-1000hdx-cap", &adv_1000hdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001557 if (status)
1558 goto nxge_map_myargs_to_gmii_fail4;
1559
1560 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001561 "adv-100fdx-cap", &adv_100fdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001562 if (status)
1563 goto nxge_map_myargs_to_gmii_fail5;
1564
1565 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001566 "adv-100hdx-cap", &adv_100hdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001567 if (status)
1568 goto nxge_map_myargs_to_gmii_fail6;
1569
1570 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001571 "adv-10fdx-cap", &adv_10fdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001572 if (status)
1573 goto nxge_map_myargs_to_gmii_fail7;
1574
1575 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
misaki52ccf842008-06-20 15:53:36 -07001576 "adv-10hdx-cap", &adv_10hdx_cap, 1);
girish44961712006-11-22 11:47:19 -08001577 if (status)
1578 goto nxge_map_myargs_to_gmii_fail8;
1579
speera3c5bd62007-01-30 11:29:19 -08001580 return;
girish44961712006-11-22 11:47:19 -08001581
1582nxge_map_myargs_to_gmii_fail9:
1583 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap");
1584
1585nxge_map_myargs_to_gmii_fail8:
1586 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap");
1587
1588nxge_map_myargs_to_gmii_fail7:
1589 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap");
1590
1591nxge_map_myargs_to_gmii_fail6:
1592 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap");
1593
1594nxge_map_myargs_to_gmii_fail5:
1595 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap");
1596
1597nxge_map_myargs_to_gmii_fail4:
1598 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap");
1599
1600nxge_map_myargs_to_gmii_fail3:
1601 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap");
1602
1603nxge_map_myargs_to_gmii_fail2:
1604 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap");
1605
1606nxge_map_myargs_to_gmii_fail1:
1607 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap");
girish44961712006-11-22 11:47:19 -08001608}
1609
girish44961712006-11-22 11:47:19 -08001610nxge_status_t
1611nxge_get_config_properties(p_nxge_t nxgep)
1612{
speera3c5bd62007-01-30 11:29:19 -08001613 nxge_status_t status = NXGE_OK;
1614 p_nxge_hw_list_t hw_p;
Janie Lu4df55fd2009-12-11 10:41:17 -08001615 char **prop_val;
1616 uint_t prop_len;
1617 uint_t i;
girish44961712006-11-22 11:47:19 -08001618
1619 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties"));
1620
1621 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1622 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -07001623 " nxge_get_config_properties:"
1624 " common hardware not set", nxgep->niu_type));
girish44961712006-11-22 11:47:19 -08001625 return (NXGE_ERROR);
1626 }
1627
1628 /*
1629 * Get info on how many ports Neptune card has.
1630 */
raghus2e591292007-08-31 16:49:49 -07001631 nxgep->nports = nxge_get_nports(nxgep);
davemq59ac0c12007-07-25 18:20:14 -07001632 if (nxgep->nports <= 0) {
1633 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1634 "<==nxge_get_config_properties: Invalid Neptune type 0x%x",
1635 nxgep->niu_type));
1636 return (NXGE_ERROR);
1637 }
1638 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY;
raghus2e591292007-08-31 16:49:49 -07001639 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1640 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY;
1641 }
davemq59ac0c12007-07-25 18:20:14 -07001642 if (nxgep->function_num >= nxgep->nports) {
1643 return (NXGE_ERROR);
girish44961712006-11-22 11:47:19 -08001644 }
1645
sd7746814ea4bb2006-12-22 12:42:28 -08001646 status = nxge_get_mac_addr_properties(nxgep);
speera3c5bd62007-01-30 11:29:19 -08001647 if (status != NXGE_OK)
sd7746814ea4bb2006-12-22 12:42:28 -08001648 return (NXGE_ERROR);
speera3c5bd62007-01-30 11:29:19 -08001649
1650 /*
1651 * read the configuration type. If none is specified, used default.
1652 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM
1653 * are shared equally across all the ports.
1654 *
speer58324df2007-02-22 15:55:32 -08001655 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional
1656 * to the port speed.
speera3c5bd62007-01-30 11:29:19 -08001657 *
1658 *
1659 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is
1660 * specified in nxge.conf. Need to read each parameter and set
1661 * up the parameters in nxge structures.
1662 *
1663 */
girish44961712006-11-22 11:47:19 -08001664 switch (nxgep->niu_type) {
speera3c5bd62007-01-30 11:29:19 -08001665 case N2_NIU:
1666 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
misaki52ccf842008-06-20 15:53:36 -07001667 " ==> nxge_get_config_properties: N2"));
speera3c5bd62007-01-30 11:29:19 -08001668 MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1669 if ((hw_p->flags & COMMON_CFG_VALID) !=
misaki52ccf842008-06-20 15:53:36 -07001670 COMMON_CFG_VALID) {
speera3c5bd62007-01-30 11:29:19 -08001671 status = nxge_cfg_verify_set(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001672 COMMON_RXDMA_GRP_CFG);
speera3c5bd62007-01-30 11:29:19 -08001673 status = nxge_cfg_verify_set(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001674 COMMON_CLASS_CFG);
speera3c5bd62007-01-30 11:29:19 -08001675 hw_p->flags |= COMMON_CFG_VALID;
1676 }
1677 MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1678 status = nxge_use_cfg_n2niu_properties(nxgep);
1679 break;
davemq59ac0c12007-07-25 18:20:14 -07001680 default:
raghus2e591292007-08-31 16:49:49 -07001681 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
davemq59ac0c12007-07-25 18:20:14 -07001682 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1683 " nxge_get_config_properties:"
1684 " unknown NIU type 0x%x", nxgep->niu_type));
1685 return (NXGE_ERROR);
1686 }
girish44961712006-11-22 11:47:19 -08001687
speera3c5bd62007-01-30 11:29:19 -08001688 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
misaki52ccf842008-06-20 15:53:36 -07001689 " ==> nxge_get_config_properties: Neptune"));
speera3c5bd62007-01-30 11:29:19 -08001690 status = nxge_cfg_verify_set_quick_config(nxgep);
1691 MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1692 if ((hw_p->flags & COMMON_CFG_VALID) !=
misaki52ccf842008-06-20 15:53:36 -07001693 COMMON_CFG_VALID) {
speera3c5bd62007-01-30 11:29:19 -08001694 status = nxge_cfg_verify_set(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001695 COMMON_TXDMA_CFG);
speera3c5bd62007-01-30 11:29:19 -08001696 status = nxge_cfg_verify_set(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001697 COMMON_RXDMA_CFG);
speera3c5bd62007-01-30 11:29:19 -08001698 status = nxge_cfg_verify_set(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001699 COMMON_RXDMA_GRP_CFG);
speera3c5bd62007-01-30 11:29:19 -08001700 status = nxge_cfg_verify_set(nxgep,
misaki52ccf842008-06-20 15:53:36 -07001701 COMMON_CLASS_CFG);
speera3c5bd62007-01-30 11:29:19 -08001702 hw_p->flags |= COMMON_CFG_VALID;
1703 }
1704 MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1705 nxge_use_cfg_neptune_properties(nxgep);
1706 status = NXGE_OK;
1707 break;
girish44961712006-11-22 11:47:19 -08001708 }
1709
ml296233d16f8e2008-02-13 13:10:16 -08001710 /*
1711 * Get the software LSO enable flag property from the
1712 * driver configuration file (nxge.conf).
1713 * This flag will be set to disable (0) if this property
1714 * does not exist.
1715 */
1716 nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip,
1717 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "soft-lso-enable", 0);
1718 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1719 "nxge_get_config_properties: software lso %d\n",
1720 nxgep->soft_lso_enable));
1721
Janie Lu4df55fd2009-12-11 10:41:17 -08001722 nxgep->niu_hw_type = NIU_HW_TYPE_DEFAULT;
1723 if (nxgep->niu_type == N2_NIU) {
Santwona Behera9d587972010-05-20 10:19:34 -07001724
1725 uchar_t *s_prop_val;
1726
Janie Lu4df55fd2009-12-11 10:41:17 -08001727 /*
1728 * For NIU, the next generation KT has
1729 * a few differences in features that the
1730 * driver needs to handle them
1731 * accordingly.
1732 */
1733 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1734 "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1735 for (i = 0; i < prop_len; i++) {
1736 if ((strcmp((caddr_t)prop_val[i],
1737 KT_NIU_COMPATIBLE) == 0)) {
1738 nxgep->niu_hw_type = NIU_HW_TYPE_RF;
1739 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1740 "NIU type %d", nxgep->niu_hw_type));
1741 break;
1742 }
1743 }
1744 }
1745
1746 ddi_prop_free(prop_val);
Santwona Behera9d587972010-05-20 10:19:34 -07001747 /*
1748 * Some Serdes and PHY properties may also be provided as OBP
1749 * properties
1750 */
1751 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1752 "tx-cfg-l", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1753 nxgep->srds_prop.tx_cfg_l =
1754 (uint16_t)(*(uint32_t *)s_prop_val);
1755 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1756 "nxge_get_config_properties: "
1757 "tx_cfg_l 0x%x, Read from OBP",
1758 nxgep->srds_prop.tx_cfg_l));
1759 nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGL;
1760 ddi_prop_free(s_prop_val);
1761 }
1762 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1763 "tx-cfg-h", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1764 nxgep->srds_prop.tx_cfg_h =
1765 (uint16_t)(*(uint32_t *)s_prop_val);
1766 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1767 "nxge_get_config_properties: "
1768 "tx_cfg_h 0x%x, Read from OBP",
1769 nxgep->srds_prop.tx_cfg_h));
1770 nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGH;
1771 ddi_prop_free(s_prop_val);
1772 }
1773 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1774 "rx-cfg-l", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1775 nxgep->srds_prop.rx_cfg_l =
1776 (uint16_t)(*(uint32_t *)s_prop_val);
1777 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1778 "nxge_get_config_properties: "
1779 "rx_cfg_l 0x%x, Read from OBP",
1780 nxgep->srds_prop.rx_cfg_l));
1781 nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGL;
1782 ddi_prop_free(s_prop_val);
1783 }
1784 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1785 "rx-cfg-h", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1786 nxgep->srds_prop.rx_cfg_h =
1787 (uint16_t)(*(uint32_t *)s_prop_val);
1788 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1789 "nxge_get_config_properties: "
1790 "rx_cfg_h 0x%x, Read from OBP",
1791 nxgep->srds_prop.rx_cfg_h));
1792 nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGH;
1793 ddi_prop_free(s_prop_val);
1794 }
1795 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1796 "pll-cfg", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1797 nxgep->srds_prop.pll_cfg_l =
1798 (uint16_t)(*(uint32_t *)s_prop_val);
1799 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1800 "nxge_get_config_properties: "
1801 "pll_cfg_l 0x%x, Read from OBP",
1802 nxgep->srds_prop.pll_cfg_l));
1803 nxgep->srds_prop.prop_set |= NXGE_SRDS_PLLCFGL;
1804 ddi_prop_free(s_prop_val);
1805 }
1806 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1807 "phy-reg-values", &s_prop_val, &prop_len) ==
1808 DDI_PROP_SUCCESS) {
1809
1810 int tun_cnt, i;
1811 uchar_t *arr = s_prop_val;
1812
1813 tun_cnt = prop_len / 6; /* 3 values, 2 bytes each */
1814 nxgep->phy_prop.arr =
1815 KMEM_ZALLOC(sizeof (nxge_phy_mdio_val_t) * tun_cnt,
1816 KM_SLEEP);
1817 nxgep->phy_prop.cnt = tun_cnt;
1818 for (i = 0; i < tun_cnt; i++) {
1819 nxgep->phy_prop.arr[i].dev = *(uint16_t *)arr;
1820 arr += 2;
1821 nxgep->phy_prop.arr[i].reg = *(uint16_t *)arr;
1822 arr += 2;
1823 nxgep->phy_prop.arr[i].val = *(uint16_t *)arr;
1824 arr += 2;
1825 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1826 "nxge_get_config_properties: From OBP, "
1827 "read PHY <dev.reg.val> = "
1828 "<0x%x.0x%x.0x%x>",
1829 nxgep->phy_prop.arr[i].dev,
1830 nxgep->phy_prop.arr[i].reg,
1831 nxgep->phy_prop.arr[i].val));
1832 }
1833 ddi_prop_free(s_prop_val);
1834 }
Janie Lu4df55fd2009-12-11 10:41:17 -08001835 }
1836
girish44961712006-11-22 11:47:19 -08001837 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties"));
1838 return (status);
1839}
1840
girish44961712006-11-22 11:47:19 -08001841static nxge_status_t
1842nxge_use_cfg_n2niu_properties(p_nxge_t nxgep)
1843{
1844 nxge_status_t status = NXGE_OK;
1845
1846 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties"));
1847
1848 status = nxge_use_default_dma_config_n2(nxgep);
1849 if (status != NXGE_OK) {
1850 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
misaki52ccf842008-06-20 15:53:36 -07001851 " ==> nxge_use_cfg_n2niu_properties (err 0x%x)",
1852 status));
girish44961712006-11-22 11:47:19 -08001853 return (status | NXGE_ERROR);
1854 }
1855
1856 (void) nxge_use_cfg_vlan_class_config(nxgep);
1857 (void) nxge_use_cfg_mac_class_config(nxgep);
1858 (void) nxge_use_cfg_class_config(nxgep);
girish44961712006-11-22 11:47:19 -08001859 (void) nxge_use_cfg_link_cfg(nxgep);
1860
girish44961712006-11-22 11:47:19 -08001861 /*
speera3c5bd62007-01-30 11:29:19 -08001862 * Read in the hardware (fcode) properties. Use the ndd array to read
1863 * each property.
girish44961712006-11-22 11:47:19 -08001864 */
1865 (void) nxge_get_param_soft_properties(nxgep);
1866 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties"));
1867
1868 return (status);
1869}
1870
girish44961712006-11-22 11:47:19 -08001871static void
1872nxge_use_cfg_neptune_properties(p_nxge_t nxgep)
1873{
speera3c5bd62007-01-30 11:29:19 -08001874 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties"));
girish44961712006-11-22 11:47:19 -08001875
1876 (void) nxge_use_cfg_dma_config(nxgep);
1877 (void) nxge_use_cfg_vlan_class_config(nxgep);
1878 (void) nxge_use_cfg_mac_class_config(nxgep);
1879 (void) nxge_use_cfg_class_config(nxgep);
girish44961712006-11-22 11:47:19 -08001880 (void) nxge_use_cfg_link_cfg(nxgep);
1881
girish44961712006-11-22 11:47:19 -08001882 /*
speera3c5bd62007-01-30 11:29:19 -08001883 * Read in the hardware (fcode) properties. Use the ndd array to read
1884 * each property.
girish44961712006-11-22 11:47:19 -08001885 */
1886 (void) nxge_get_param_soft_properties(nxgep);
speera3c5bd62007-01-30 11:29:19 -08001887 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties"));
girish44961712006-11-22 11:47:19 -08001888}
1889
speera3c5bd62007-01-30 11:29:19 -08001890/*
Michael Speer952a2462009-03-11 16:27:24 -07001891 * FWARC 2006/556 for N2 NIU. Get the properties
1892 * from the prom.
speera3c5bd62007-01-30 11:29:19 -08001893 */
girish44961712006-11-22 11:47:19 -08001894static nxge_status_t
1895nxge_use_default_dma_config_n2(p_nxge_t nxgep)
1896{
Michael Speer952a246