| /* |
| * This file and its contents are supplied under the terms of the |
| * Common Development and Distribution License ("CDDL"), version 1.0. |
| * You may only use this file in accordance with the terms of version |
| * 1.0 of the CDDL. |
| * |
| * A full copy of the text of the CDDL should have accompanied this |
| * source. A copy of the CDDL is also available via the Internet at |
| * http://www.illumos.org/license/CDDL. |
| */ |
| |
| /* |
| * This file is part of the Chelsio T4/T5/T6 Ethernet driver. |
| * |
| * Copyright (C) 2003-2019 Chelsio Communications. All rights reserved. |
| * |
| * This program is distributed in the hope that it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this |
| * release for licensing terms and conditions. |
| */ |
| |
| /* |
| * Copyright 2020 RackTop Systems, Inc. |
| */ |
| |
| #include "common.h" |
| #include "t4_regs.h" |
| #include "t4_regs_values.h" |
| #include "t4fw_interface.h" |
| |
| /** |
| * t4_wait_op_done_val - wait until an operation is completed |
| * @adapter: the adapter performing the operation |
| * @reg: the register to check for completion |
| * @mask: a single-bit field within @reg that indicates completion |
| * @polarity: the value of the field when the operation is completed |
| * @attempts: number of check iterations |
| * @delay: delay in usecs between iterations |
| * @valp: where to store the value of the register at completion time |
| * |
| * Wait until an operation is completed by checking a bit in a register |
| * up to @attempts times. If @valp is not NULL the value of the register |
| * at the time it indicated completion is stored there. Returns 0 if the |
| * operation completes and -EAGAIN otherwise. |
| */ |
| static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, |
| int polarity, int attempts, int delay, u32 *valp) |
| { |
| while (1) { |
| u32 val = t4_read_reg(adapter, reg); |
| |
| if (!!(val & mask) == polarity) { |
| if (valp) |
| *valp = val; |
| return 0; |
| } |
| if (--attempts == 0) |
| return -EAGAIN; |
| if (delay) |
| udelay(delay); |
| } |
| } |
| |
| static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, |
| int polarity, int attempts, int delay) |
| { |
| return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, |
| delay, NULL); |
| } |
| |
| /** |
| * t4_set_reg_field - set a register field to a value |
| * @adapter: the adapter to program |
| * @addr: the register address |
| * @mask: specifies the portion of the register to modify |
| * @val: the new value for the register field |
| * |
| * Sets a register field specified by the supplied mask to the |
| * given value. |
| */ |
| void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, |
| u32 val) |
| { |
| u32 v = t4_read_reg(adapter, addr) & ~mask; |
| |
| t4_write_reg(adapter, addr, v | val); |
| (void) t4_read_reg(adapter, addr); /* flush */ |
| } |
| |
| /** |
| * t4_read_indirect - read indirectly addressed registers |
| * @adap: the adapter |
| * @addr_reg: register holding the indirect address |
| * @data_reg: register holding the value of the indirect register |
| * @vals: where the read register values are stored |
| * @nregs: how many indirect registers to read |
| * @start_idx: index of first indirect register to read |
| * |
| * Reads registers that are accessed indirectly through an address/data |
| * register pair. |
| */ |
| void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, |
| unsigned int data_reg, u32 *vals, |
| unsigned int nregs, unsigned int start_idx) |
| { |
| while (nregs--) { |
| t4_write_reg(adap, addr_reg, start_idx); |
| *vals++ = t4_read_reg(adap, data_reg); |
| start_idx++; |
| } |
| } |
| |
| /** |
| * t4_write_indirect - write indirectly addressed registers |
| * @adap: the adapter |
| * @addr_reg: register holding the indirect addresses |
| * @data_reg: register holding the value for the indirect registers |
| * @vals: values to write |
| * @nregs: how many indirect registers to write |
| * @start_idx: address of first indirect register to write |
| * |
| * Writes a sequential block of registers that are accessed indirectly |
| * through an address/data register pair. |
| */ |
| void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, |
| unsigned int data_reg, const u32 *vals, |
| unsigned int nregs, unsigned int start_idx) |
| { |
| while (nregs--) { |
| t4_write_reg(adap, addr_reg, start_idx++); |
| t4_write_reg(adap, data_reg, *vals++); |
| } |
| } |
| |
| /* |
| * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor |
| * mechanism. This guarantees that we get the real value even if we're |
| * operating within a Virtual Machine and the Hypervisor is trapping our |
| * Configuration Space accesses. |
| * |
| * N.B. This routine should only be used as a last resort: the firmware uses |
| * the backdoor registers on a regular basis and we can end up |
| * conflicting with it's uses! |
| */ |
| void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) |
| { |
| u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); |
| |
| if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) |
| req |= F_ENABLE; |
| else |
| req |= F_T6_ENABLE; |
| |
| if (is_t4(adap->params.chip)) |
| req |= F_LOCALCFG; |
| |
| t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); |
| *val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); |
| |
| /* Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a |
| * Configuration Space read. (None of the other fields matter when |
| * F_ENABLE is 0 so a simple register write is easier than a |
| * read-modify-write via t4_set_reg_field().) |
| */ |
| t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); |
| } |
| |
| /* |
| * t4_report_fw_error - report firmware error |
| * @adap: the adapter |
| * |
| * The adapter firmware can indicate error conditions to the host. |
| * If the firmware has indicated an error, print out the reason for |
| * the firmware error. |
| */ |
| static void t4_report_fw_error(struct adapter *adap) |
| { |
| static const char *const reason[] = { |
| "Crash", /* PCIE_FW_EVAL_CRASH */ |
| "During Device Preparation", /* PCIE_FW_EVAL_PREP */ |
| "During Device Configuration", /* PCIE_FW_EVAL_CONF */ |
| "During Device Initialization", /* PCIE_FW_EVAL_INIT */ |
| "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ |
| "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ |
| "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ |
| "Reserved", /* reserved */ |
| }; |
| u32 pcie_fw; |
| |
| pcie_fw = t4_read_reg(adap, A_PCIE_FW); |
| if (pcie_fw & F_PCIE_FW_ERR) { |
| CH_ERR(adap, "Firmware reports adapter error: %s\n", |
| reason[G_PCIE_FW_EVAL(pcie_fw)]); |
| adap->flags &= ~FW_OK; |
| } |
| } |
| |
| /* |
| * Get the reply to a mailbox command and store it in @rpl in big-endian order. |
| */ |
| static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, |
| u32 mbox_addr) |
| { |
| for ( ; nflit; nflit--, mbox_addr += 8) |
| *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); |
| } |
| |
| /* |
| * Handle a FW assertion reported in a mailbox. |
| */ |
| static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) |
| { |
| CH_ALERT(adap, |
| "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", |
| asrt->u.assert.filename_0_7, |
| be32_to_cpu(asrt->u.assert.line), |
| be32_to_cpu(asrt->u.assert.x), |
| be32_to_cpu(asrt->u.assert.y)); |
| } |
| |
| #define X_CIM_PF_NOACCESS 0xeeeeeeee |
| |
| /* |
| * If the OS Driver wants busy waits to keep a watchdog happy, tap it during |
| * busy loops which don't sleep. |
| */ |
| #ifdef T4_OS_NEEDS_TOUCH_NMI_WATCHDOG |
| #define T4_OS_TOUCH_NMI_WATCHDOG() t4_os_touch_nmi_watchdog() |
| #else |
| #define T4_OS_TOUCH_NMI_WATCHDOG() |
| #endif |
| |
| #ifdef T4_OS_LOG_MBOX_CMDS |
| /** |
| * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log |
| * @adapter: the adapter |
| * @cmd: the Firmware Mailbox Command or Reply |
| * @size: command length in bytes |
| * @access: the time (ms) needed to access the Firmware Mailbox |
| * @execute: the time (ms) the command spent being executed |
| */ |
| static void t4_record_mbox(struct adapter *adapter, |
| const __be64 *cmd, unsigned int size, |
| int access, int execute) |
| { |
| struct mbox_cmd_log *log = adapter->mbox_log; |
| struct mbox_cmd *entry; |
| int i; |
| |
| entry = mbox_cmd_log_entry(log, log->cursor++); |
| if (log->cursor == log->size) |
| log->cursor = 0; |
| |
| for (i = 0; i < size/8; i++) |
| entry->cmd[i] = be64_to_cpu(cmd[i]); |
| while (i < MBOX_LEN/8) |
| entry->cmd[i++] = 0; |
| entry->timestamp = t4_os_timestamp(); |
| entry->seqno = log->seqno++; |
| entry->access = access; |
| entry->execute = execute; |
| } |
| |
| #define T4_RECORD_MBOX(__adapter, __cmd, __size, __access, __execute) \ |
| t4_record_mbox(__adapter, __cmd, __size, __access, __execute) |
| |
| #else /* !T4_OS_LOG_MBOX_CMDS */ |
| |
| #define T4_RECORD_MBOX(__adapter, __cmd, __size, __access, __execute) \ |
| /* nothing */ |
| |
| #endif /* !T4_OS_LOG_MBOX_CMDS */ |
| |
| /** |
| * t4_record_mbox_marker - record a marker in the mailbox log |
| * @adapter: the adapter |
| * @marker: byte array marker |
| * @size: marker size in bytes |
| * |
| * We inject a "fake mailbox command" into the Firmware Mailbox Log |
| * using a known command token and then the bytes of the specified |
| * marker. This lets debugging code inject markers into the log to |
| * help identify which commands are in response to higher level code. |
| */ |
| void t4_record_mbox_marker(struct adapter *adapter, |
| const void *marker, unsigned int size) |
| { |
| #ifdef T4_OS_LOG_MBOX_CMDS |
| __be64 marker_cmd[MBOX_LEN/8]; |
| const unsigned int max_marker = sizeof marker_cmd - sizeof (__be64); |
| unsigned int marker_cmd_size; |
| |
| if (size > max_marker) |
| size = max_marker; |
| |
| marker_cmd[0] = cpu_to_be64(~0LLU); |
| memcpy(&marker_cmd[1], marker, size); |
| memset((unsigned char *)&marker_cmd[1] + size, 0, max_marker - size); |
| marker_cmd_size = sizeof (__be64) + roundup(size, sizeof (__be64)); |
| |
| t4_record_mbox(adapter, marker_cmd, marker_cmd_size, 0, 0); |
| #endif /* T4_OS_LOG_MBOX_CMDS */ |
| } |
| |
| /* |
| * Delay time in microseconds to wait for mailbox access/fw reply |
| * to mailbox command |
| */ |
| #define MIN_MBOX_CMD_DELAY 900 |
| #define MBOX_CMD_DELAY 1000 |
| |
| /** |
| * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox |
| * @adap: the adapter |
| * @mbox: index of the mailbox to use |
| * @cmd: the command to write |
| * @size: command length in bytes |
| * @rpl: where to optionally store the reply |
| * @sleep_ok: if true we may sleep while awaiting command completion |
| * @timeout: time to wait for command to finish before timing out |
| * (negative implies @sleep_ok=false) |
| * |
| * Sends the given command to FW through the selected mailbox and waits |
| * for the FW to execute the command. If @rpl is not %NULL it is used to |
| * store the FW's reply to the command. The command and its optional |
| * reply are of the same length. Some FW commands like RESET and |
| * INITIALIZE can take a considerable amount of time to execute. |
| * @sleep_ok determines whether we may sleep while awaiting the response. |
| * If sleeping is allowed we use progressive backoff otherwise we spin. |
| * Note that passing in a negative @timeout is an alternate mechanism |
| * for specifying @sleep_ok=false. This is useful when a higher level |
| * interface allows for specification of @timeout but not @sleep_ok ... |
| * |
| * The return value is 0 on success or a negative errno on failure. A |
| * failure can happen either because we are not able to execute the |
| * command or FW executes it but signals an error. In the latter case |
| * the return value is the error code indicated by FW (negated). |
| */ |
| int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, |
| int size, void *rpl, bool sleep_ok, int timeout) |
| { |
| #ifdef T4_OS_LOG_MBOX_CMDS |
| u16 access = 0; |
| #endif /* T4_OS_LOG_MBOX_CMDS */ |
| u32 v; |
| u64 res; |
| int i, ret; |
| const __be64 *p = cmd; |
| u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); |
| u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); |
| u32 ctl; |
| __be64 cmd_rpl[MBOX_LEN/8]; |
| struct t4_mbox_list entry; |
| u32 pcie_fw; |
| |
| if ((size & 15) || size > MBOX_LEN) |
| return -EINVAL; |
| |
| /* |
| * If we have a negative timeout, that implies that we can't sleep. |
| */ |
| if (timeout < 0) { |
| sleep_ok = false; |
| timeout = -timeout; |
| } |
| |
| /* |
| * Queue ourselves onto the mailbox access list. When our entry is at |
| * the front of the list, we have rights to access the mailbox. So we |
| * wait [for a while] till we're at the front [or bail out with an |
| * EBUSY] ... |
| */ |
| t4_mbox_list_add(adap, &entry); |
| |
| for (i = 0; ; i++) { |
| /* |
| * If we've waited too long, return a busy indication. This |
| * really ought to be based on our initial position in the |
| * mailbox access list but this is a start. We very rarely |
| * contend on access to the mailbox ... Also check for a |
| * firmware error which we'll report as a device error. |
| */ |
| pcie_fw = t4_read_reg(adap, A_PCIE_FW); |
| if (i > 4*timeout || (pcie_fw & F_PCIE_FW_ERR)) { |
| t4_mbox_list_del(adap, &entry); |
| t4_report_fw_error(adap); |
| ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY; |
| T4_RECORD_MBOX(adap, cmd, size, ret, 0); |
| return ret; |
| } |
| |
| /* |
| * If we're at the head, break out and start the mailbox |
| * protocol. |
| */ |
| if (t4_mbox_list_first_entry(adap) == &entry) |
| break; |
| |
| /* |
| * Delay for a bit before checking again ... |
| */ |
| if (sleep_ok) { |
| usleep_range(MIN_MBOX_CMD_DELAY, MBOX_CMD_DELAY); |
| } else { |
| T4_OS_TOUCH_NMI_WATCHDOG(); |
| udelay(MBOX_CMD_DELAY); |
| } |
| } |
| #ifdef T4_OS_LOG_MBOX_CMDS |
| access = i; |
| #endif /* T4_OS_LOG_MBOX_CMDS */ |
| |
| /* |
| * Attempt to gain access to the mailbox. |
| */ |
| for (i = 0; i < 4; i++) { |
| ctl = t4_read_reg(adap, ctl_reg); |
| v = G_MBOWNER(ctl); |
| if (v != X_MBOWNER_NONE) |
| break; |
| } |
| |
| /* |
| * If we were unable to gain access, dequeue ourselves from the |
| * mailbox atomic access list and report the error to our caller. |
| */ |
| if (v != X_MBOWNER_PL) { |
| t4_mbox_list_del(adap, &entry); |
| t4_report_fw_error(adap); |
| ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; |
| T4_RECORD_MBOX(adap, cmd, size, access, ret); |
| return ret; |
| } |
| |
| /* |
| * If we gain ownership of the mailbox and there's a "valid" message |
| * in it, this is likely an asynchronous error message from the |
| * firmware. So we'll report that and then proceed on with attempting |
| * to issue our own command ... which may well fail if the error |
| * presaged the firmware crashing ... |
| */ |
| if (ctl & F_MBMSGVALID) { |
| CH_ERR(adap, "found VALID command in mbox %u: " |
| "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, |
| (unsigned long long)t4_read_reg64(adap, data_reg), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 8), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 16), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 24), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 32), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 40), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 48), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 56)); |
| } |
| |
| /* |
| * Copy in the new mailbox command and send it on its way ... |
| */ |
| T4_RECORD_MBOX(adap, cmd, size, access, 0); |
| for (i = 0; i < size; i += 8, p++) |
| t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); |
| |
| /* |
| * XXX It's not clear that we need this anymore now |
| * XXX that we have mailbox logging ... |
| */ |
| CH_DUMP_MBOX(adap, mbox, data_reg, size / 8); |
| |
| t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); |
| (void) t4_read_reg(adap, ctl_reg); /* flush write */ |
| |
| /* |
| * Loop waiting for the reply; bail out if we time out or the firmware |
| * reports an error. |
| */ |
| for (i = 0; |
| !((pcie_fw = t4_read_reg(adap, A_PCIE_FW)) & F_PCIE_FW_ERR) && |
| i < timeout; |
| i++) { |
| if (sleep_ok) { |
| usleep_range(MIN_MBOX_CMD_DELAY, MBOX_CMD_DELAY); |
| } else { |
| T4_OS_TOUCH_NMI_WATCHDOG(); |
| udelay(MBOX_CMD_DELAY); |
| } |
| |
| v = t4_read_reg(adap, ctl_reg); |
| if (v == X_CIM_PF_NOACCESS) |
| continue; |
| if (G_MBOWNER(v) == X_MBOWNER_PL) { |
| if (!(v & F_MBMSGVALID)) { |
| t4_write_reg(adap, ctl_reg, |
| V_MBOWNER(X_MBOWNER_NONE)); |
| continue; |
| } |
| |
| /* |
| * Retrieve the command reply and release the mailbox. |
| */ |
| get_mbox_rpl(adap, cmd_rpl, size/8, data_reg); |
| t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); |
| t4_mbox_list_del(adap, &entry); |
| |
| T4_RECORD_MBOX(adap, cmd_rpl, size, access, i + 1); |
| |
| /* |
| * XXX It's not clear that we need this anymore now |
| * XXX that we have mailbox logging ... |
| */ |
| CH_DUMP_MBOX(adap, mbox, data_reg, size / 8); |
| CH_MSG(adap, INFO, HW, |
| "command completed in %d ms (%ssleeping)\n", |
| i + 1, sleep_ok ? "" : "non-"); |
| |
| res = be64_to_cpu(cmd_rpl[0]); |
| if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { |
| fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); |
| res = V_FW_CMD_RETVAL(EIO); |
| } else if (rpl) |
| memcpy(rpl, cmd_rpl, size); |
| return -G_FW_CMD_RETVAL((int)res); |
| } |
| } |
| |
| /* |
| * We timed out waiting for a reply to our mailbox command. Report |
| * the error and also check to see if the firmware reported any |
| * errors ... |
| */ |
| t4_mbox_list_del(adap, &entry); |
| |
| ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; |
| T4_RECORD_MBOX(adap, cmd, size, access, ret); |
| CH_ERR(adap, "command 0x%x in mailbox %d timed out\n", |
| *(const u8 *)cmd, mbox); |
| |
| t4_report_fw_error(adap); |
| t4_fatal_err(adap); |
| return ret; |
| } |
| |
| #ifdef CONFIG_CUDBG |
| /* |
| * The maximum number of times to iterate for FW reply before |
| * issuing a mailbox timeout |
| */ |
| #define FW_REPLY_WAIT_LOOP 6000000 |
| |
| /** |
| * t4_wr_mbox_meat_timeout_panic - send a command to FW through the given |
| * mailbox. This function is a minimal version of t4_wr_mbox_meat_timeout() |
| * and is only invoked during a kernel crash. Since this function is |
| * called through a atomic notifier chain ,we cannot sleep awaiting a |
| * response from FW, hence repeatedly loop until we get a reply. |
| * |
| * @adap: the adapter |
| * @mbox: index of the mailbox to use |
| * @cmd: the command to write |
| * @size: command length in bytes |
| * @rpl: where to optionally store the reply |
| */ |
| |
| static int t4_wr_mbox_meat_timeout_panic(struct adapter *adap, int mbox, |
| const void *cmd, int size, void *rpl) |
| { |
| u32 v; |
| u64 res; |
| int i, ret; |
| u64 cnt; |
| const __be64 *p = cmd; |
| u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); |
| u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); |
| u32 ctl; |
| __be64 cmd_rpl[MBOX_LEN/8]; |
| u32 pcie_fw; |
| |
| if ((size & 15) || size > MBOX_LEN) |
| return -EINVAL; |
| |
| /* |
| * Check for a firmware error which we'll report as a |
| * device error. |
| */ |
| pcie_fw = t4_read_reg(adap, A_PCIE_FW); |
| if (pcie_fw & F_PCIE_FW_ERR) { |
| t4_report_fw_error(adap); |
| ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY; |
| return ret; |
| } |
| |
| /* |
| * Attempt to gain access to the mailbox. |
| */ |
| for (i = 0; i < 4; i++) { |
| ctl = t4_read_reg(adap, ctl_reg); |
| v = G_MBOWNER(ctl); |
| if (v != X_MBOWNER_NONE) |
| break; |
| } |
| |
| /* |
| * If we were unable to gain access, report the error to our caller. |
| */ |
| if (v != X_MBOWNER_PL) { |
| t4_report_fw_error(adap); |
| ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; |
| return ret; |
| } |
| |
| /* |
| * If we gain ownership of the mailbox and there's a "valid" message |
| * in it, this is likely an asynchronous error message from the |
| * firmware. So we'll report that and then proceed on with attempting |
| * to issue our own command ... which may well fail if the error |
| * presaged the firmware crashing ... |
| */ |
| if (ctl & F_MBMSGVALID) { |
| CH_ERR(adap, "found VALID command in mbox %u: " |
| "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, |
| (unsigned long long)t4_read_reg64(adap, data_reg), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 8), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 16), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 24), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 32), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 40), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 48), |
| (unsigned long long)t4_read_reg64(adap, data_reg + 56)); |
| } |
| |
| /* |
| * Copy in the new mailbox command and send it on its way ... |
| */ |
| for (i = 0; i < size; i += 8, p++) |
| t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); |
| |
| CH_DUMP_MBOX(adap, mbox, data_reg, size / 8); |
| |
| t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); |
| t4_read_reg(adap, ctl_reg); /* flush write */ |
| |
| /* |
| * Loop waiting for the reply; bail out if we time out or the firmware |
| * reports an error. |
| */ |
| for (cnt = 0; |
| !((pcie_fw = t4_read_reg(adap, A_PCIE_FW)) & F_PCIE_FW_ERR) && |
| cnt < FW_REPLY_WAIT_LOOP; |
| cnt++) { |
| v = t4_read_reg(adap, ctl_reg); |
| if (v == X_CIM_PF_NOACCESS) |
| continue; |
| if (G_MBOWNER(v) == X_MBOWNER_PL) { |
| if (!(v & F_MBMSGVALID)) { |
| t4_write_reg(adap, ctl_reg, |
| V_MBOWNER(X_MBOWNER_NONE)); |
| continue; |
| } |
| |
| /* |
| * Retrieve the command reply and release the mailbox. |
| */ |
| get_mbox_rpl(adap, cmd_rpl, size/8, data_reg); |
| t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); |
| |
| CH_DUMP_MBOX(adap, mbox, data_reg, size / 8); |
| |
| res = be64_to_cpu(cmd_rpl[0]); |
| if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { |
| fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); |
| res = V_FW_CMD_RETVAL(EIO); |
| } else if (rpl) |
| memcpy(rpl, cmd_rpl, size); |
| return -G_FW_CMD_RETVAL((int)res); |
| } |
| } |
| |
| /* |
| * We timed out waiting for a reply to our mailbox command. Report |
| * the error and also check to see if the firmware reported any |
| * errors ... |
| */ |
| ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; |
| CH_ERR(adap, "command %#x in mailbox %d timed out\n", |
| *(const u8 *)cmd, mbox); |
| |
| t4_report_fw_error(adap); |
| t4_fatal_err(adap); |
| return ret; |
| } |
| #endif |
| |
| int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, |
| void *rpl, bool sleep_ok) |
| { |
| #ifdef CONFIG_CUDBG |
| if (adap->flags & K_CRASH) |
| return t4_wr_mbox_meat_timeout_panic(adap, mbox, cmd, size, |
| rpl); |
| else |
| #endif |
| return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, |
| sleep_ok, FW_CMD_MAX_TIMEOUT); |
| |
| } |
| |
| static int t4_edc_err_read(struct adapter *adap, int idx) |
| { |
| u32 edc_ecc_err_addr_reg; |
| u32 edc_bist_status_rdata_reg; |
| |
| if (is_t4(adap->params.chip)) { |
| CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); |
| return 0; |
| } |
| if (idx != MEM_EDC0 && idx != MEM_EDC1) { |
| CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); |
| return 0; |
| } |
| |
| edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); |
| edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); |
| |
| CH_WARN(adap, |
| "edc%d err addr 0x%x: 0x%x.\n", |
| idx, edc_ecc_err_addr_reg, |
| t4_read_reg(adap, edc_ecc_err_addr_reg)); |
| CH_WARN(adap, |
| "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", |
| edc_bist_status_rdata_reg, |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), |
| (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); |
| |
| return 0; |
| } |
| |
| /** |
| * t4_memory_rw_addr - read/write adapter memory via PCIE memory window |
| * @adap: the adapter |
| * @win: PCI-E Memory Window to use |
| * @addr: address within adapter memory |
| * @len: amount of memory to transfer |
| * @hbuf: host memory buffer |
| * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0) |
| * |
| * Reads/writes an [almost] arbitrary memory region in the firmware: the |
| * firmware memory address and host buffer must be aligned on 32-bit |
| * boudaries; the length may be arbitrary. |
| * |
| * NOTES: |
| * 1. The memory is transferred as a raw byte sequence from/to the |
| * firmware's memory. If this memory contains data structures which |
| * contain multi-byte integers, it's the caller's responsibility to |
| * perform appropriate byte order conversions. |
| * |
| * 2. It is the Caller's responsibility to ensure that no other code |
| * uses the specified PCI-E Memory Window while this routine is |
| * using it. This is typically done via the use of OS-specific |
| * locks, etc. |
| */ |
| int t4_memory_rw_addr(struct adapter *adap, int win, u32 addr, |
| u32 len, void *hbuf, int dir) |
| { |
| u32 pos, offset, resid; |
| u32 win_pf, mem_reg, mem_aperture, mem_base; |
| u32 *buf; |
| |
| /* Argument sanity checks ... |
| */ |
| if (addr & 0x3 || (uintptr_t)hbuf & 0x3) |
| return -EINVAL; |
| buf = (u32 *)hbuf; |
| |
| /* It's convenient to be able to handle lengths which aren't a |
| * multiple of 32-bits because we often end up transferring files to |
| * the firmware. So we'll handle that by normalizing the length here |
| * and then handling any residual transfer at the end. |
| */ |
| resid = len & 0x3; |
| len -= resid; |
| |
| /* Each PCI-E Memory Window is programmed with a window size -- or |
| * "aperture" -- which controls the granularity of its mapping onto |
| * adapter memory. We need to grab that aperture in order to know |
| * how to use the specified window. The window is also programmed |
| * with the base address of the Memory Window in BAR0's address |
| * space. For T4 this is an absolute PCI-E Bus Address. For T5 |
| * the address is relative to BAR0. |
| */ |
| mem_reg = t4_read_reg(adap, |
| PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, |
| win)); |
| |
| /* a dead adapter will return 0xffffffff for PIO reads */ |
| if (mem_reg == 0xffffffff) { |
| CH_WARN(adap, "Unable to read PCI-E Memory Window Base[%d]\n", |
| win); |
| return -ENXIO; |
| } |
| |
| mem_aperture = 1 << (G_WINDOW(mem_reg) + X_WINDOW_SHIFT); |
| mem_base = G_PCIEOFST(mem_reg) << X_PCIEOFST_SHIFT; |
| if (is_t4(adap->params.chip)) |
| mem_base -= adap->t4_bar0; |
| win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->pf); |
| |
| /* Calculate our initial PCI-E Memory Window Position and Offset into |
| * that Window. |
| */ |
| pos = addr & ~(mem_aperture-1); |
| offset = addr - pos; |
| |
| /* Set up initial PCI-E Memory Window to cover the start of our |
| * transfer. (Read it back to ensure that changes propagate before we |
| * attempt to use the new value.) |
| */ |
| t4_write_reg(adap, |
| PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, win), |
| pos | win_pf); |
| t4_read_reg(adap, |
| PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, win)); |
| |
| /* Transfer data to/from the adapter as long as there's an integral |
| * number of 32-bit transfers to complete. |
| * |
| * A note on Endianness issues: |
| * |
| * The "register" reads and writes below from/to the PCI-E Memory |
| * Window invoke the standard adapter Big-Endian to PCI-E Link |
| * Little-Endian "swizzel." As a result, if we have the following |
| * data in adapter memory: |
| * |
| * Memory: ... | b0 | b1 | b2 | b3 | ... |
| * Address: i+0 i+1 i+2 i+3 |
| * |
| * Then a read of the adapter memory via the PCI-E Memory Window |
| * will yield: |
| * |
| * x = readl(i) |
| * 31 0 |
| * [ b3 | b2 | b1 | b0 ] |
| * |
| * If this value is stored into local memory on a Little-Endian system |
| * it will show up correctly in local memory as: |
| * |
| * ( ..., b0, b1, b2, b3, ... ) |
| * |
| * But on a Big-Endian system, the store will show up in memory |
| * incorrectly swizzled as: |
| * |
| * ( ..., b3, b2, b1, b0, ... ) |
| * |
| * So we need to account for this in the reads and writes to the |
| * PCI-E Memory Window below by undoing the register read/write |
| * swizzels. |
| */ |
| while (len > 0) { |
| if (dir == T4_MEMORY_READ) |
| *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, |
| mem_base + offset)); |
| else |
| t4_write_reg(adap, mem_base + offset, |
| (__force u32)cpu_to_le32(*buf++)); |
| offset += sizeof(__be32); |
| len -= sizeof(__be32); |
| |
| /* If we've reached the end of our current window aperture, |
| * move the PCI-E Memory Window on to the next. Note that |
| * doing this here after "len" may be 0 allows us to set up |
| * the PCI-E Memory Window for a possible final residual |
| * transfer below ... |
| */ |
| if (offset == mem_aperture) { |
| pos += mem_aperture; |
| offset = 0; |
| t4_write_reg(adap, |
| PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, |
| win), pos | win_pf); |
| t4_read_reg(adap, |
| PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, |
| win)); |
| } |
| } |
| |
| /* If the original transfer had a length which wasn't a multiple of |
| * 32-bits, now's where we need to finish off the transfer of the |
| * residual amount. The PCI-E Memory Window has already been moved |
| * above (if necessary) to cover this final transfer. |
| */ |
| if (resid) { |
| union { |
| u32 word; |
| char byte[4]; |
| } last; |
| unsigned char *bp; |
| int i; |
| |
| if (dir == T4_MEMORY_READ) { |
| last.word = le32_to_cpu( |
| (__force __le32)t4_read_reg(adap, |
| mem_base + offset)); |
| for (bp = (unsigned char *)buf, i = resid; i < 4; i++) |
| bp[i] = last.byte[i]; |
| } else { |
| last.word = *buf; |
| for (i = resid; i < 4; i++) |
| last.byte[i] = 0; |
| t4_write_reg(adap, mem_base + offset, |
| (__force u32)cpu_to_le32(last.word)); |
| } |
| } |
| |
| return 0; |
| } |
| |
| /** |
| * t4_memory_rw_mtype - read/write EDC 0, EDC 1 or MC via PCIE memory window |
| * @adap: the adapter |
| * @win: PCI-E Memory Window to use |
| * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC |
| * @maddr: address within indicated memory type |
| * @len: amount of memory to transfer |
| * @hbuf: host memory buffer |
| * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0) |
| * |
| * Reads/writes adapter memory using t4_memory_rw_addr(). This routine |
| * provides an (memory type, address withing memory type) interface. |
| */ |
| int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr, |
| u32 len, void *hbuf, int dir) |
| { |
| u32 mtype_offset; |
| u32 edc_size, mc_size; |
| |
| /* Offset into the region of memory which is being accessed |
| * MEM_EDC0 = 0 |
| * MEM_EDC1 = 1 |
| * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller |
| * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5) |
| * MEM_HMA = 4 |
| */ |
| edc_size = G_EDRAM0_SIZE(t4_read_reg(adap, A_MA_EDRAM0_BAR)); |
| if (mtype == MEM_HMA) { |
| mtype_offset = 2 * (edc_size * 1024 * 1024); |
| } else if (mtype != MEM_MC1) |
| mtype_offset = (mtype * (edc_size * 1024 * 1024)); |
| else { |
| mc_size = G_EXT_MEM0_SIZE(t4_read_reg(adap, |
| A_MA_EXT_MEMORY0_BAR)); |
| mtype_offset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; |
| } |
| |
| return t4_memory_rw_addr(adap, win, |
| mtype_offset + maddr, len, |
| hbuf, dir); |
| } |
| |
| /* |
| * Return the specified PCI-E Configuration Space register from our Physical |
| * Function. We try first via a Firmware LDST Command (if fw_attach != 0) |
| * since we prefer to let the firmware own all of these registers, but if that |
| * fails we go for it directly ourselves. |
| */ |
| u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) |
| { |
| u32 val; |
| |
| /* |
| * If fw_attach != 0, construct and send the Firmware LDST Command to |
| * retrieve the specified PCI-E Configuration Space register. |
| */ |
| if (drv_fw_attach != 0) { |
| struct fw_ldst_cmd ldst_cmd; |
| int ret; |
| |
| memset(&ldst_cmd, 0, sizeof(ldst_cmd)); |
| ldst_cmd.op_to_addrspace = |
| cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | |
| F_FW_CMD_REQUEST | |
| F_FW_CMD_READ | |
| V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); |
| ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); |
| ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); |
| ldst_cmd.u.pcie.ctrl_to_fn = |
| (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); |
| ldst_cmd.u.pcie.r = reg; |
| |
| /* |
| * If the LDST Command succeeds, return the result, otherwise |
| * fall through to reading it directly ourselves ... |
| */ |
| ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), |
| &ldst_cmd); |
| if (ret == 0) |
| return be32_to_cpu(ldst_cmd.u.pcie.data[0]); |
| |
| CH_WARN(adap, "Firmware failed to return " |
| "Configuration Space register %d, err = %d\n", |
| reg, -ret); |
| } |
| |
| /* |
| * Read the desired Configuration Space register via the PCI-E |
| * Backdoor mechanism. |
| */ |
| t4_hw_pci_read_cfg4(adap, reg, &val); |
| return val; |
| } |
| |
| /* |
| * Get the window based on base passed to it. |
| * Window aperture is currently unhandled, but there is no use case for it |
| * right now |
| */ |
| static int t4_get_window(struct adapter *adap, u64 pci_base, u64 pci_mask, u64 memwin_base, int drv_fw_attach) |
| { |
| if (is_t4(adap->params.chip)) { |
| u32 bar0; |
| |
| /* |
| * Truncation intentional: we only read the bottom 32-bits of |
| * the 64-bit BAR0/BAR1 ... We use the hardware backdoor |
| * mechanism to read BAR0 instead of using |
| * pci_resource_start() because we could be operating from |
| * within a Virtual Machine which is trapping our accesses to |
| * our Configuration Space and we need to set up the PCI-E |
| * Memory Window decoders with the actual addresses which will |
| * be coming across the PCI-E link. |
| */ |
| bar0 = t4_read_pcie_cfg4(adap, pci_base, drv_fw_attach); |
| bar0 &= pci_mask; |
| adap->t4_bar0 = bar0; |
| |
| return bar0 + memwin_base; |
| } else { |
| /* For T5, only relative offset inside the PCIe BAR is passed */ |
| return memwin_base; |
| } |
| } |
| |
| /* Get the default utility window (win0) used by everyone */ |
| int t4_get_util_window(struct adapter *adap, int drv_fw_attach) |
| { |
| return t4_get_window(adap, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE, drv_fw_attach); |
| } |
| |
| /* |
| * Set up memory window for accessing adapter memory ranges. (Read |
| * back MA register to ensure that changes propagate before we attempt |
| * to use the new values.) |
| */ |
| void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window) |
| { |
| t4_write_reg(adap, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, window), |
| memwin_base | V_BIR(0) | |
| V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); |
| t4_read_reg(adap, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, window)); |
| } |
| |
| /** |
| * t4_get_regs_len - return the size of the chips register set |
| * @adapter: the adapter |
| * |
| * Returns the size of the chip's BAR0 register space. |
| */ |
| unsigned int t4_get_regs_len(struct adapter *adapter) |
| { |
| unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); |
| |
| switch (chip_version) { |
| case CHELSIO_T4: |
| return T4_REGMAP_SIZE; |
| |
| case CHELSIO_T5: |
| case CHELSIO_T6: |
| return T5_REGMAP_SIZE; |
| } |
| |
| CH_ERR(adapter, |
| "Unsupported chip version %d\n", chip_version); |
| return 0; |
| } |
| |
| /** |
| * t4_get_regs - read chip registers into provided buffer |
| * @adap: the adapter |
| * @buf: register buffer |
| * @buf_size: size (in bytes) of register buffer |
| * |
| * If the provided register buffer isn't large enough for the chip's |
| * full register range, the register dump will be truncated to the |
| * register buffer's size. |
| */ |
| void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) |
| { |
| static const unsigned int t4_reg_ranges[] = { |
| 0x1008, 0x1108, |
| 0x1180, 0x1184, |
| 0x1190, 0x1194, |
| 0x11a0, 0x11a4, |
| 0x11b0, 0x11b4, |
| 0x11fc, 0x123c, |
| 0x1300, 0x173c, |
| 0x1800, 0x18fc, |
| 0x3000, 0x30d8, |
| 0x30e0, 0x30e4, |
| 0x30ec, 0x5910, |
| 0x5920, 0x5924, |
| 0x5960, 0x5960, |
| 0x5968, 0x5968, |
| 0x5970, 0x5970, |
| 0x5978, 0x5978, |
| 0x5980, 0x5980, |
| 0x5988, 0x5988, |
| 0x5990, 0x5990, |
| 0x5998, 0x5998, |
| 0x59a0, 0x59d4, |
| 0x5a00, 0x5ae0, |
| 0x5ae8, 0x5ae8, |
| 0x5af0, 0x5af0, |
| 0x5af8, 0x5af8, |
| 0x6000, 0x6098, |
| 0x6100, 0x6150, |
| 0x6200, 0x6208, |
| 0x6240, 0x6248, |
| 0x6280, 0x62b0, |
| 0x62c0, 0x6338, |
| 0x6370, 0x638c, |
| 0x6400, 0x643c, |
| 0x6500, 0x6524, |
| 0x6a00, 0x6a04, |
| 0x6a14, 0x6a38, |
| 0x6a60, 0x6a70, |
| 0x6a78, 0x6a78, |
| 0x6b00, 0x6b0c, |
| 0x6b1c, 0x6b84, |
| 0x6bf0, 0x6bf8, |
| 0x6c00, 0x6c0c, |
| 0x6c1c, 0x6c84, |
| 0x6cf0, 0x6cf8, |
| 0x6d00, 0x6d0c, |
| 0x6d1c, 0x6d84, |
| 0x6df0, 0x6df8, |
| 0x6e00, 0x6e0c, |
| 0x6e1c, 0x6e84, |
| 0x6ef0, 0x6ef8, |
| 0x6f00, 0x6f0c, |
| 0x6f1c, 0x6f84, |
| 0x6ff0, 0x6ff8, |
| 0x7000, 0x700c, |
| 0x701c, 0x7084, |
| 0x70f0, 0x70f8, |
| 0x7100, 0x710c, |
| 0x711c, 0x7184, |
| 0x71f0, 0x71f8, |
| 0x7200, 0x720c, |
| 0x721c, 0x7284, |
| 0x72f0, 0x72f8, |
| 0x7300, 0x730c, |
| 0x731c, 0x7384, |
| 0x73f0, 0x73f8, |
| 0x7400, 0x7450, |
| 0x7500, 0x7530, |
| 0x7600, 0x760c, |
| 0x7614, 0x761c, |
| 0x7680, 0x76cc, |
| 0x7700, 0x7798, |
| 0x77c0, 0x77fc, |
| 0x7900, 0x79fc, |
| 0x7b00, 0x7b58, |
| 0x7b60, 0x7b84, |
| 0x7b8c, 0x7c38, |
| 0x7d00, 0x7d38, |
| 0x7d40, 0x7d80, |
| 0x7d8c, 0x7ddc, |
| 0x7de4, 0x7e04, |
| 0x7e10, 0x7e1c, |
| 0x7e24, 0x7e38, |
| 0x7e40, 0x7e44, |
| 0x7e4c, 0x7e78, |
| 0x7e80, 0x7ea4, |
| 0x7eac, 0x7edc, |
| 0x7ee8, 0x7efc, |
| 0x8dc0, 0x8e04, |
| 0x8e10, 0x8e1c, |
| 0x8e30, 0x8e78, |
| 0x8ea0, 0x8eb8, |
| 0x8ec0, 0x8f6c, |
| 0x8fc0, 0x9008, |
| 0x9010, 0x9058, |
| 0x9060, 0x9060, |
| 0x9068, 0x9074, |
| 0x90fc, 0x90fc, |
| 0x9400, 0x9408, |
| 0x9410, 0x9458, |
| 0x9600, 0x9600, |
| 0x9608, 0x9638, |
| 0x9640, 0x96bc, |
| 0x9800, 0x9808, |
| 0x9820, 0x983c, |
| 0x9850, 0x9864, |
| 0x9c00, 0x9c6c, |
| 0x9c80, 0x9cec, |
| 0x9d00, 0x9d6c, |
| 0x9d80, 0x9dec, |
| 0x9e00, 0x9e6c, |
| 0x9e80, 0x9eec, |
| 0x9f00, 0x9f6c, |
| 0x9f80, 0x9fec, |
| 0xd004, 0xd004, |
| 0xd010, 0xd03c, |
| 0xdfc0, 0xdfe0, |
| 0xe000, 0xea7c, |
| 0xf000, 0x11110, |
| 0x11118, 0x11190, |
| 0x19040, 0x1906c, |
| 0x19078, 0x19080, |
| 0x1908c, 0x190e4, |
| 0x190f0, 0x190f8, |
| 0x19100, 0x19110, |
| 0x19120, 0x19124, |
| 0x19150, 0x19194, |
| 0x1919c, 0x191b0, |
| 0x191d0, 0x191e8, |
| 0x19238, 0x1924c, |
| 0x193f8, 0x1943c, |
| 0x1944c, 0x19474, |
| 0x19490, 0x194e0, |
| 0x194f0, 0x194f8, |
| 0x19800, 0x19c08, |
| 0x19c10, 0x19c90, |
| 0x19ca0, 0x19ce4, |
| 0x19cf0, 0x19d40, |
| 0x19d50, 0x19d94, |
| 0x19da0, 0x19de8, |
| 0x19df0, 0x19e40, |
| 0x19e50, 0x19e90, |
| 0x19ea0, 0x19f4c, |
| 0x1a000, 0x1a004, |
| 0x1a010, 0x1a06c, |
| 0x1a0b0, 0x1a0e4, |
| 0x1a0ec, 0x1a0f4, |
| 0x1a100, 0x1a108, |
| 0x1a114, 0x1a120, |
| 0x1a128, 0x1a130, |
| 0x1a138, 0x1a138, |
| 0x1a190, 0x1a1c4, |
| 0x1a1fc, 0x1a1fc, |
| 0x1e040, 0x1e04c, |
| 0x1e284, 0x1e28c, |
| 0x1e2c0, 0x1e2c0, |
| 0x1e2e0, 0x1e2e0, |
| 0x1e300, 0x1e384, |
| 0x1e3c0, 0x1e3c8, |
| 0x1e440, 0x1e44c, |
| 0x1e684, 0x1e68c, |
| 0x1e6c0, 0x1e6c0, |
| 0x1e6e0, 0x1e6e0, |
| 0x1e700, 0x1e784, |
| 0x1e7c0, 0x1e7c8, |
| 0x1e840, 0x1e84c, |
| 0x1ea84, 0x1ea8c, |
| 0x1eac0, 0x1eac0, |
| 0x1eae0, 0x1eae0, |
| 0x1eb00, 0x1eb84, |
| 0x1ebc0, 0x1ebc8, |
| 0x1ec40, 0x1ec4c, |
| 0x1ee84, 0x1ee8c, |
| 0x1eec0, 0x1eec0, |
| 0x1eee0, 0x1eee0, |
| 0x1ef00, 0x1ef84, |
| 0x1efc0, 0x1efc8, |
| 0x1f040, 0x1f04c, |
| 0x1f284, 0x1f28c, |
| 0x1f2c0, 0x1f2c0, |
| 0x1f2e0, 0x1f2e0, |
| 0x1f300, 0x1f384, |
| 0x1f3c0, 0x1f3c8, |
| 0x1f440, 0x1f44c, |
| 0x1f684, 0x1f68c, |
| 0x1f6c0, 0x1f6c0, |
| 0x1f6e0, 0x1f6e0, |
| 0x1f700, 0x1f784, |
| 0x1f7c0, 0x1f7c8, |
| 0x1f840, 0x1f84c, |
| 0x1fa84, 0x1fa8c, |
| 0x1fac0, 0x1fac0, |
| 0x1fae0, 0x1fae0, |
| 0x1fb00, 0x1fb84, |
| 0x1fbc0, 0x1fbc8, |
| 0x1fc40, 0x1fc4c, |
| 0x1fe84, 0x1fe8c, |
| 0x1fec0, 0x1fec0, |
| 0x1fee0, 0x1fee0, |
| 0x1ff00, 0x1ff84, |
| 0x1ffc0, 0x1ffc8, |
| 0x20000, 0x2002c, |
| 0x20100, 0x2013c, |
| 0x20190, 0x201a0, |
| 0x201a8, 0x201b8, |
| 0x201c4, 0x201c8, |
| 0x20200, 0x20318, |
| 0x20400, 0x204b4, |
| 0x204c0, 0x20528, |
| 0x20540, 0x20614, |
| 0x21000, 0x21040, |
| 0x2104c, 0x21060, |
| 0x210c0, 0x210ec, |
| 0x21200, 0x21268, |
| 0x21270, 0x21284, |
| 0x212fc, 0x21388, |
| 0x21400, 0x21404, |
| 0x21500, 0x21500, |
| 0x21510, 0x21518, |
| 0x2152c, 0x21530, |
| 0x2153c, 0x2153c, |
| 0x21550, 0x21554, |
| 0x21600, 0x21600, |
| 0x21608, 0x2161c, |
| 0x21624, 0x21628, |
| 0x21630, 0x21634, |
| 0x2163c, 0x2163c, |
| 0x21700, 0x2171c, |
| 0x21780, 0x2178c, |
| 0x21800, 0x21818, |
| 0x21820, 0x21828, |
| 0x21830, 0x21848, |
| 0x21850, 0x21854, |
| 0x21860, 0x21868, |
| 0x21870, 0x21870, |
| 0x21878, 0x21898, |
| 0x218a0, 0x218a8, |
| 0x218b0, 0x218c8, |
| 0x218d0, 0x218d4, |
| 0x218e0, 0x218e8, |
| 0x218f0, 0x218f0, |
| 0x218f8, 0x21a18, |
| 0x21a20, 0x21a28, |
| 0x21a30, 0x21a48, |
| 0x21a50, 0x21a54, |
| 0x21a60, 0x21a68, |
| 0x21a70, 0x21a70, |
| 0x21a78, 0x21a98, |
| 0x21aa0, 0x21aa8, |
| 0x21ab0, 0x21ac8, |
| 0x21ad0, 0x21ad4, |
| 0x21ae0, 0x21ae8, |
| 0x21af0, 0x21af0, |
| 0x21af8, 0x21c18, |
| 0x21c20, 0x21c20, |
| 0x21c28, 0x21c30, |
| 0x21c38, 0x21c38, |
| 0x21c80, 0x21c98, |
| 0x21ca0, 0x21ca8, |
| 0x21cb0, 0x21cc8, |
| 0x21cd0, 0x21cd4, |
| 0x21ce0, 0x21ce8, |
| 0x21cf0, 0x21cf0, |
| 0x21cf8, 0x21d7c, |
| 0x21e00, 0x21e04, |
| 0x22000, 0x2202c, |
| 0x22100, 0x2213c, |
| 0x22190, 0x221a0, |
| 0x221a8, 0x221b8, |
| 0x221c4, 0x221c8, |
| 0x22200, 0x22318, |
| 0x22400, 0x224b4, |
| 0x224c0, 0x22528, |
| 0x22540, 0x22614, |
| 0x23000, 0x23040, |
| 0x2304c, 0x23060, |
| 0x230c0, 0x230ec, |
| 0x23200, 0x23268, |
| 0x23270, 0x23284, |
| 0x232fc, 0x23388, |
| 0x23400, 0x23404, |
| 0x23500, 0x23500, |
| 0x23510, 0x23518, |
| 0x2352c, 0x23530, |
| 0x2353c, 0x2353c, |
| 0x23550, 0x23554, |
| 0x23600, 0x23600, |
| 0x23608, 0x2361c, |
| 0x23624, 0x23628, |
| 0x23630, 0x23634, |
| 0x2363c, 0x2363c, |
| 0x23700, 0x2371c, |
| 0x23780, 0x2378c, |
| 0x23800, 0x23818, |
| 0x23820, 0x23828, |
| 0x23830, 0x23848, |
| 0x23850, 0x23854, |
| 0x23860, 0x23868, |
| 0x23870, 0x23870, |
| 0x23878, 0x23898, |
| 0x238a0, 0x238a8, |
| 0x238b0, 0x238c8, |
| 0x238d0, 0x238d4, |
| 0x238e0, 0x238e8, |
| 0x238f0, 0x238f0, |
| 0x238f8, 0x23a18, |
| 0x23a20, 0x23a28, |
| 0x23a30, 0x23a48, |
| 0x23a50, 0x23a54, |
| 0x23a60, 0x23a68, |
| 0x23a70, 0x23a70, |
| 0x23a78, 0x23a98, |
| 0x23aa0, 0x23aa8, |
| 0x23ab0, 0x23ac8, |
| 0x23ad0, 0x23ad4, |
| 0x23ae0, 0x23ae8, |
| 0x23af0, 0x23af0, |
| 0x23af8, 0x23c18, |
| 0x23c20, 0x23c20, |
| 0x23c28, 0x23c30, |
| 0x23c38, 0x23c38, |
| 0x23c80, 0x23c98, |
| 0x23ca0, 0x23ca8, |
| 0x23cb0, 0x23cc8, |
| 0x23cd0, 0x23cd4, |
| 0x23ce0, 0x23ce8, |
| 0x23cf0, 0x23cf0, |
| 0x23cf8, 0x23d7c, |
| 0x23e00, 0x23e04, |
| 0x24000, 0x2402c, |
| 0x24100, 0x2413c, |
| 0x24190, 0x241a0, |
| 0x241a8, 0x241b8, |
| 0x241c4, 0x241c8, |
| 0x24200, 0x24318, |
| 0x24400, 0x244b4, |
| 0x244c0, 0x24528, |
| 0x24540, 0x24614, |
| 0x25000, 0x25040, |
| 0x2504c, 0x25060, |
| 0x250c0, 0x250ec, |
| 0x25200, 0x25268, |
| 0x25270, 0x25284, |
| 0x252fc, 0x25388, |
| 0x25400, 0x25404, |
| 0x25500, 0x25500, |
| 0x25510, 0x25518, |
| 0x2552c, 0x25530, |
| 0x2553c, 0x2553c, |
| 0x25550, 0x25554, |
| 0x25600, 0x25600, |
| 0x25608, 0x2561c, |
| 0x25624, 0x25628, |
| 0x25630, 0x25634, |
| 0x2563c, 0x2563c, |
| 0x25700, 0x2571c, |
| 0x25780, 0x2578c, |
| 0x25800, 0x25818, |
| 0x25820, 0x25828, |
| 0x25830, 0x25848, |
| 0x25850, 0x25854, |
| 0x25860, 0x25868, |
| 0x25870, 0x25870, |
| 0x25878, 0x25898, |
| 0x258a0, 0x258a8, |
| 0x258b0, 0x258c8, |
| 0x258d0, 0x258d4, |
| 0x258e0, 0x258e8, |
| 0x258f0, 0x258f0, |
| 0x258f8, 0x25a18, |
| 0x25a20, 0x25a28, |
| 0x25a30, 0x25a48, |
| 0x25a50, 0x25a54, |
| 0x25a60, 0x25a68, |
| 0x25a70, 0x25a70, |
| 0x25a78, 0x25a98, |
| 0x25aa0, 0x25aa8, |
| 0x25ab0, 0x25ac8, |
| 0x25ad0, 0x25ad4, |
| 0x25ae0, 0x25ae8, |
| 0x25af0, 0x25af0, |
| 0x25af8, 0x25c18, |
| 0x25c20, 0x25c20, |
| 0x25c28, 0x25c30, |
| 0x25c38, 0x25c38, |
| 0x25c80, 0x25c98, |
| 0x25ca0, 0x25ca8, |
| 0x25cb0, 0x25cc8, |
| 0x25cd0, 0x25cd4, |
| 0x25ce0, 0x25ce8, |
| 0x25cf0, 0x25cf0, |
| 0x25cf8, 0x25d7c, |
| 0x25e00, 0x25e04, |
| 0x26000, 0x2602c, |
| 0x26100, 0x2613c, |
| 0x26190, 0x261a0, |
| 0x261a8, 0x261b8, |
| 0x261c4, 0x261c8, |
| 0x26200, 0x26318, |
| 0x26400, 0x264b4, |
| 0x264c0, 0x26528, |
| 0x26540, 0x26614, |
| 0x27000, 0x27040, |
| 0x2704c, 0x27060, |
| 0x270c0, 0x270ec, |
| 0x27200, 0x27268, |
| 0x27270, 0x27284, |
| 0x272fc, 0x27388, |
| 0x27400, 0x27404, |
| 0x27500, 0x27500, |
| 0x27510, 0x27518, |
| 0x2752c, 0x27530, |
| 0x2753c, 0x2753c, |
| 0x27550, 0x27554, |
| 0x27600, 0x27600, |
| 0x27608, 0x2761c, |
| 0x27624, 0x27628, |
| 0x27630, 0x27634, |
| 0x2763c, 0x2763c, |
| 0x27700, 0x2771c, |
| 0x27780, 0x2778c, |
| 0x27800, 0x27818, |
| 0x27820, 0x27828, |
| 0x27830, 0x27848, |
| 0x27850, 0x27854, |
| 0x27860, 0x27868, |
| 0x27870, 0x27870, |
| 0x27878, 0x27898, |
| 0x278a0, 0x278a8, |
| 0x278b0, 0x278c8, |
| 0x278d0, 0x278d4, |
| 0x278e0, 0x278e8, |
| 0x278f0, 0x278f0, |
| 0x278f8, 0x27a18, |
| 0x27a20, 0x27a28, |
| 0x27a30, 0x27a48, |
| 0x27a50, 0x27a54, |
| 0x27a60, 0x27a68, |
| 0x27a70, 0x27a70, |
| 0x27a78, 0x27a98, |
| 0x27aa0, 0x27aa8, |
| 0x27ab0, 0x27ac8, |
| 0x27ad0, 0x27ad4, |
| 0x27ae0, 0x27ae8, |
| 0x27af0, 0x27af0, |
| 0x27af8, 0x27c18, |
| 0x27c20, 0x27c20, |
| 0x27c28, 0x27c30, |
| 0x27c38, 0x27c38, |
| 0x27c80, 0x27c98, |
| 0x27ca0, 0x27ca8, |
| 0x27cb0, 0x27cc8, |
| 0x27cd0, 0x27cd4, |
| 0x27ce0, 0x27ce8, |
| 0x27cf0, 0x27cf0, |
| 0x27cf8, 0x27d7c, |
| 0x27e00, 0x27e04, |
| }; |
| |
| static const unsigned int t5_reg_ranges[] = { |
| 0x1008, 0x10c0, |
| 0x10cc, 0x10f8, |
| 0x1100, 0x1100, |
| 0x110c, 0x1148, |
| 0x1180, 0x1184, |
| 0x1190, 0x1194, |
| 0x11a0, 0x11a4, |
| 0x11b0, 0x11b4, |
| 0x11fc, 0x123c, |
| 0x1280, 0x173c, |
| 0x1800, 0x18fc, |
| 0x3000, 0x3028, |
| 0x3060, 0x30b0, |
| 0x30b8, 0x30d8, |
| 0x30e0, 0x30fc, |
| 0x3140, 0x357c, |
| 0x35a8, 0x35cc, |
| 0x35ec, 0x35ec, |
| 0x3600, 0x5624, |
| 0x56cc, 0x56ec, |
| 0x56f4, 0x5720, |
| 0x5728, 0x575c, |
| 0x580c, 0x5814, |
| 0x5890, 0x589c, |
| 0x58a4, 0x58ac, |
| 0x58b8, 0x58bc, |
| 0x5940, 0x59c8, |
| 0x59d0, 0x59dc, |
| 0x59fc, 0x5a18, |
| 0x5a60, 0x5a70, |
| 0x5a80, 0x5a9c, |
| 0x5b94, 0x5bfc, |
| 0x6000, 0x6020, |
| 0x6028, 0x6040, |
| 0x6058, 0x609c, |
| 0x60a8, 0x614c, |
| 0x7700, 0x7798, |
| 0x77c0, 0x78fc, |
| 0x7b00, 0x7b58, |
| 0x7b60, 0x7b84, |
| 0x7b8c, 0x7c54, |
| 0x7d00, 0x7d38, |
| 0x7d40, 0x7d80, |
| 0x7d8c, 0x7ddc, |
| 0x7de4, 0x7e04, |
| 0x7e10, 0x7e1c, |
| 0x7e24, 0x7e38, |
| 0x7e40, 0x7e44, |
| 0x7e4c, 0x7e78, |
| 0x7e80, 0x7edc, |
| 0x7ee8, 0x7efc, |
| 0x8dc0, 0x8de0, |
| 0x8df8, 0x8e04, |
| 0x8e10, 0x8e84, |
| 0x8ea0, 0x8f84, |
| 0x8fc0, 0x9058, |
| 0x9060, 0x9060, |
| 0x9068, 0x90f8, |
| 0x9400, 0x9408, |
| 0x9410, 0x9470, |
| 0x9600, 0x9600, |
| 0x9608, 0x9638, |
| 0x9640, 0x96f4, |
| 0x9800, 0x9808, |
| 0x9820, 0x983c, |
| 0x9850, 0x9864, |
| 0x9c00, 0x9c6c, |
| 0x9c80, 0x9cec, |
| 0x9d00, 0x9d6c, |
| 0x9d80, 0x9dec, |
| 0x9e00, 0x9e6c, |
| 0x9e80, 0x9eec, |
| 0x9f00, 0x9f6c, |
| 0x9f80, 0xa020, |
| 0xd004, 0xd004, |
| 0xd010, 0xd03c, |
| 0xdfc0, 0xdfe0, |
| 0xe000, 0x1106c, |
| 0x11074, 0x11088, |
| 0x1109c, 0x1117c, |
| 0x11190, 0x11204, |
| 0x19040, 0x1906c, |
| 0x19078, 0x19080, |
| 0x1908c, 0x190e8, |
| 0x190f0, 0x190f8, |
| 0x19100, 0x19110, |
| 0x19120, 0x19124, |
| 0x19150, 0x19194, |
| 0x1919c, 0x191b0, |
| 0x191d0, 0x191e8, |
| 0x19238, 0x19290, |
| 0x193f8, 0x19428, |
| 0x19430, 0x19444, |
| 0x1944c, 0x1946c, |
| 0x19474, 0x19474, |
| 0x19490, 0x194cc, |
| 0x194f0, 0x194f8, |
| 0x19c00, 0x19c08, |
| 0x19c10, 0x19c60, |
| 0x19c94, 0x19ce4, |
| 0x19cf0, 0x19d40, |
| 0x19d50, 0x19d94, |
| 0x19da0, 0x19de8, |
| 0x19df0, 0x19e10, |
| 0x19e50, 0x19e90, |
| 0x19ea0, 0x19f24, |
| 0x19f34, 0x19f34, |
| 0x19f40, 0x19f50, |
| 0x19f90, 0x19fb4, |
| 0x19fc4, 0x19fe4, |
| 0x1a000, 0x1a004, |
| 0x1a010, 0x1a06c, |
| 0x1a0b0, 0x1a0e4, |
| 0x1a0ec, 0x1a0f8, |
| 0x1a100, 0x1a108, |
| 0x1a114, 0x1a120, |
| 0x1a128, 0x1a130, |
| 0x1a138, 0x1a138, |
| 0x1a190, 0x1a1c4, |
| 0x1a1fc, 0x1a1fc, |
| 0x1e008, 0x1e00c, |
| 0x1e040, 0x1e044, |
| 0x1e04c, 0x1e04c, |
| 0x1e284, 0x1e290, |
| 0x1e2c0, 0x1e2c0, |
| 0x1e2e0, 0x1e2e0, |
| 0x1e300, 0x1e384, |
| 0x1e3c0, 0x1e3c8, |
| 0x1e408, 0x1e40c, |
| 0x1e440, 0x1e444, |
| 0x1e44c, 0x1e44c, |
| 0x1e684, 0x1e690, |
| 0x1e6c0, 0x1e6c0, |
| 0x1e6e0, 0x1e6e0, |
| 0x1e700, 0x1e784, |
| 0x1e7c0, 0x1e7c8, |
| 0x1e808, 0x1e80c, |
| 0x1e840, 0x1e844, |
| 0x1e84c, 0x1e84c, |
| 0x1ea84, 0x1ea90, |
| 0x1eac0, 0x1eac0, |
| 0x1eae0, 0x1eae0, |
| 0x1eb00, 0x1eb84, |
| 0x1ebc0, 0x1ebc8, |
| 0x1ec08, 0x1ec0c, |
| 0x1ec40, 0x1ec44, |
| 0x1ec4c, 0x1ec4c, |
| 0x1ee84, 0x1ee90, |
| 0x1eec0, 0x1eec0, |
| 0x1eee0, 0x1eee0, |
| 0x1ef00, 0x1ef84, |
| 0x1efc0, 0x1efc8, |
| 0x1f008, 0x1f00c, |
| 0x1f040, 0x1f044, |
| 0x1f04c, 0x1f04c, |
| 0x1f284, 0x1f290, |
| 0x1f2c0, 0x1f2c0, |
| 0x1f2e0, 0x1f2e0, |
| 0x1f300, 0x1f384, |
| 0x1f3c0, 0x1f3c8, |
| 0x1f408, 0x1f40c, |
| 0x1f440, 0x1f444, |
| 0x1f44c, 0x1f44c, |
| 0x1f684, 0x1f690, |
| 0x1f6c0, 0x1f6c0, |
| 0x1f6e0, 0x1f6e0, |
| 0x1f700, 0x1f784, |
| 0x1f7c0, 0x1f7c8, |
| 0x1f808, 0x1f80c, |
| 0x1f840, 0x1f844, |
| 0x1f84c, 0x1f84c, |
| 0x1fa84, 0x1fa90, |
| 0x1fac0, 0x1fac0, |
| 0x1fae0, 0x1fae0, |
| 0x1fb00, 0x1fb84, |
| 0x1fbc0, 0x1fbc8, |
| 0x1fc08, 0x1fc0c, |
| 0x1fc40, 0x1fc44, |
| 0x1fc4c, 0x1fc4c, |
| 0x1fe84, 0x1fe90, |
| 0x1fec0, 0x1fec0, |
| 0x1fee0, 0x1fee0, |
| 0x1ff00, 0x1ff84, |
| 0x1ffc0, 0x1ffc8, |
| 0x30000, 0x30030, |
| 0x30100, 0x30144, |
| 0x30190, 0x301a0, |
| 0x301a8, 0x301b8, |
| 0x301c4, 0x301c8, |
| 0x301d0, 0x301d0, |
| 0x30200, 0x30318, |
| 0x30400, 0x304b4, |
| 0x304c0, 0x3052c, |
| 0x30540, 0x3061c, |
| 0x30800, 0x30828, |
| 0x30834, 0x30834, |
| 0x308c0, 0x30908, |
| 0x30910, 0x309ac, |
| 0x30a00, 0x30a14, |
| 0x30a1c, 0x30a2c, |
| 0x30a44, 0x30a50, |
| 0x30a74, 0x30a74, |
| 0x30a7c, 0x30afc, |
| 0x30b08, 0x30c24, |
| 0x30d00, 0x30d00, |
| 0x30d08, 0x30d14, |
| 0x30d1c, 0x30d20, |
| 0x30d3c, 0x30d3c, |
| 0x30d48, 0x30d50, |
| 0x31200, 0x3120c, |
| 0x31220, 0x31220, |
| 0x31240, 0x31240, |
| 0x31600, 0x3160c, |
| 0x31a00, 0x31a1c, |
| 0x31e00, 0x31e20, |
| 0x31e38, 0x31e3c, |
| 0x31e80, 0x31e80, |
| 0x31e88, 0x31ea8, |
| 0x31eb0, 0x31eb4, |
| 0x31ec8, 0x31ed4, |
| 0x31fb8, 0x32004, |
| 0x32200, 0x32200, |
| 0x32208, 0x32240, |
| 0x32248, 0x32280, |
| 0x32288, 0x322c0, |
| 0x322c8, 0x322fc, |
| 0x32600, 0x32630, |
| 0x32a00, 0x32abc, |
| 0x32b00, 0x32b10, |
| 0x32b20, 0x32b30, |
| 0x32b40, 0x32b50, |
| 0x32b60, 0x32b70, |
| 0x33000, 0x33028, |
| 0x33030, 0x33048, |
| 0x33060, 0x33068, |
| 0x33070, 0x3309c, |
| 0x330f0, 0x33128, |
| 0x33130, 0x33148, |
| 0x33160, 0x33168, |
| 0x33170, 0x3319c, |
| 0x331f0, 0x33238, |
| 0x33240, 0x33240, |
| 0x33248, 0x33250, |
| 0x3325c, 0x33264, |
| 0x33270, 0x332b8, |
| 0x332c0, 0x332e4, |
| 0x332f8, 0x33338, |
| 0x33340, 0x33340, |
| 0x33348, 0x33350, |
| 0x3335c, 0x33364, |
| 0x33370, 0x333b8, |
| 0x333c0, 0x333e4, |
| 0x333f8, 0x33428, |
| 0x33430, 0x33448, |
| 0x33460, 0x33468, |
| 0x33470, 0x3349c, |
| 0x334f0, 0x33528, |
| 0x33530, 0x33548, |
| 0x33560, 0x33568, |
| 0x33570, 0x3359c, |
| 0x335f0, 0x33638, |
| 0x33640, 0x33640, |
| 0x33648, 0x33650, |
| 0x3365c, 0x33664, |
| 0x33670, 0x336b8, |
| 0x336c0, 0x336e4, |
| 0x336f8, 0x33738, |
| 0x33740, 0x33740, |
| 0x33748, 0x33750, |
| 0x3375c, 0x33764, |
| 0x33770, 0x337b8, |
| 0x337c0, 0x337e4, |
| 0x337f8, 0x337fc, |
| 0x33814, 0x33814, |
| 0x3382c, 0x3382c, |
| 0x33880, 0x3388c, |
| 0x338e8, 0x338ec, |
| 0x33900, 0x33928, |
| 0x33930, 0x33948, |
| 0x33960, 0x33968, |
| 0x33970, 0x3399c, |
| 0x339f0, 0x33a38, |
| 0x33a40, 0x33a40, |
| 0x33a48, 0x33a50, |
| 0x33a5c, 0x33a64, |
| 0x33a70, 0x33ab8, |
| 0x33ac0, 0x33ae4, |
| 0x33af8, 0x33b10, |
| 0x33b28, 0x33b28, |
| 0x33b3c, 0x33b50, |
| 0x33bf0, 0x33c10, |
| 0x33c28, 0x33c28, |
| 0x33c3c, 0x33c50, |
| 0x33cf0, 0x33cfc, |
| 0x34000, 0x34030, |
| 0x34100, 0x34144, |
| 0x34190, 0x341a0, |
| 0x341a8, 0x341b8, |
| 0x341c4, 0x341c8, |
| 0x341d0, 0x341d0, |
| 0x34200, 0x34318, |
| 0x34400, 0x344b4, |
| 0x344c0, 0x3452c, |
| 0x34540, 0x3461c, |
| 0x34800, 0x34828, |
| 0x34834, 0x34834, |
| 0x348c0, 0x34908, |
| 0x34910, 0x349ac, |
| 0x34a00, 0x34a14, |
| 0x34a1c, 0x34a2c, |
| 0x34a44, 0x34a50, |
| 0x34a74, 0x34a74, |
| 0x34a7c, 0x34afc, |
| 0x34b08, 0x34c24, |
| 0x34d00, 0x34d00, |
| 0x34d08, 0x34d14, |
| 0x34d1c, 0x34d20, |
| 0x34d3c, 0x34d3c, |
| 0x34d48, 0x34d50, |
| 0x35200, 0x3520c, |
| 0x35220, 0x35220, |
| 0x35240, 0x35240, |
| 0x35600, 0x3560c, |
| 0x35a00, 0x35a1c, |
| 0x35e00, 0x35e20, |
| 0x35e38, 0x35e3c, |
| 0x35e80, 0x35e80, |
| 0x35e88, 0x35ea8, |
| 0x35eb0, 0x35eb4, |
| 0x35ec8, 0x35ed4, |
| 0x35fb8, 0x36004, |
| 0x36200, 0x36200, |
| 0x36208, 0x36240, |
| 0x36248, 0x36280, |
| 0x36288, 0x362c0, |
| 0x362c8, 0x362fc, |
| 0x36600, 0x36630, |
| 0x36a00, 0x36abc, |
| 0x36b00, 0x36b10, |
| 0x36b20, 0x36b30, |
| 0x36b40, 0x36b50, |
| 0x36b60, 0x36b70, |
| 0x37000, 0x37028, |
| 0x37030, 0x37048, |
| 0x37060, 0x37068, |
| 0x37070, 0x3709c, |
| 0x370f0, 0x37128, |
| 0x37130, 0x37148, |
| 0x37160, 0x37168, |
| 0x37170, 0x3719c, |
| 0x371f0, 0x37238, |
| 0x37240, 0x37240, |
| 0x37248, 0x37250, |
| 0x3725c, 0x37264, |
| 0x37270, 0x372b8, |
| 0x372c0, 0x372e4, |
| 0x372f8, 0x37338, |
| 0x37340, 0x37340, |
| 0x37348, 0x37350, |
| 0x3735c, 0x37364, |
| 0x37370, 0x373b8, |
| 0x373c0, 0x373e4, |
| 0x373f8, 0x37428, |
| 0x37430, 0x37448, |
| 0x37460, 0x37468, |
| 0x37470, 0x3749c, |
| 0x374f0, 0x37528, |
| 0x37530, 0x37548, |
| 0x37560, 0x37568, |
| 0x37570, 0x3759c, |
| 0x375f0, 0x37638, |
| 0x37640, 0x37640, |
| 0x37648, 0x37650, |
| 0x3765c, 0x37664, |
| 0x37670, 0x376b8, |
| 0x376c0, 0x376e4, |
| 0x376f8, 0x37738, |
| 0x37740, 0x37740, |
| 0x37748, 0x37750, |
| 0x3775c, 0x37764, |
| 0x37770, 0x377b8, |
| 0x377c0, 0x377e4, |
| 0x377f8, 0x377fc, |
| 0x37814, 0x37814, |
| 0x3782c, 0x3782c, |
| 0x37880, 0x3788c, |
| 0x378e8, 0x378ec, |
| 0x37900, 0x37928, |
| 0x37930, 0x37948, |
| 0x37960, 0x37968, |
| 0x37970, 0x3799c, |
| 0x379f0, 0x37a38, |
| 0x37a40, 0x37a40, |
| 0x37a48, 0x37a50, |
| 0x37a5c, 0x37a64, |
| 0x37a70, 0x37ab8, |
| 0x37ac0, 0x37ae4, |
| 0x37af8, 0x37b10, |
| 0x37b28, 0x37b28, |
| 0x37b3c, 0x37b50, |
| 0x37bf0, 0x37c10, |
| 0x37c28, 0x37c28, |
| 0x37c3c, 0x37c50, |
| 0x37cf0, 0x37cfc, |
| 0x38000, 0x38030, |
| 0x38100, 0x38144, |
| 0x38190, 0x381a0, |
| 0x381a8, 0x381b8, |
| 0x381c4, 0x381c8, |
| 0x381d0, 0x381d0, |
| 0x38200, 0x38318, |
| 0x38400, 0x384b4, |
| 0x384c0, 0x3852c, |
| 0x38540, 0x3861c, |
| 0x38800, 0x38828, |
| 0x38834, 0x38834, |
| 0x388c0, 0x38908, |
| 0x38910, 0x389ac, |
| 0x38a00, 0x38a14, |
| 0x38a1c, 0x38a2c, |
| 0x38a44, 0x38a50, |
| 0x38a74, 0x38a74, |
| 0x38a7c, 0x38afc, |
| 0x38b08, 0x38c24, |
| 0x38d00, 0x38d00, |
| 0x38d08, 0x38d14, |
| 0x38d1c, 0x38d20, |
| 0x38d3c, 0x38d3c, |
| 0x38d48, 0x38d50, |
| 0x39200, 0x3920c, |
| 0x39220, 0x39220, |
| 0x39240, 0x39240, |
| 0x39600, 0x3960c, |
| 0x39a00, 0x39a1c, |
| 0x39e00, 0x39e20, |
| 0x39e38, 0x39e3c, |
| 0x39e80, 0x39e80, |
| 0x39e88, 0x39ea8, |
| 0x39eb0, 0x39eb4, |
| 0x39ec8, 0x39ed4, |
| 0x39fb8, 0x3a004, |
| 0x3a200, 0x3a200, |
| 0x3a208, 0x3a240, |
| 0x3a248, 0x3a280, |
| 0x3a288, 0x3a2c0, |
| 0x3a2c8, 0x3a2fc, |
| 0x3a600, 0x3a630, |
| 0x3aa00, 0x3aabc, |
| 0x3ab00, 0x3ab10, |
| 0x3ab20, 0x3ab30, |
| 0x3ab40, 0x3ab50, |
| 0x3ab60, 0x3ab70, |
| 0x3b000, 0x3b028, |
| 0x3b030, 0x3b048, |
| 0x3b060, 0x3b068, |
| 0x3b070, 0x3b09c, |
| 0x3b0f0, 0x3b128, |
| 0x3b130, 0x3b148, |
| 0x3b160, 0x3b168, |
| 0x3b170, 0x3b19c, |
| 0x3b1f0, 0x3b238, |
| 0x3b240, 0x3b240, |
| 0x3b248, 0x3b250, |
| 0x3b25c, 0x3b264, |
| 0x3b270, 0x3b2b8, |
| 0x3b2c0, 0x3b2e4, |
| 0x3b2f8, 0x3b338, |
| 0x3b340, 0x3b340, |
| 0x3b348, 0x3b350, |
| 0x3b35c, 0x3b364, |
| 0x3b370, 0x3b3b8, |
| 0x3b3c0, 0x3b3e4, |
| 0x3b3f8, 0x3b428, |
| 0x3b430, 0x3b448, |
| 0x3b460, 0x3b468, |
| 0x3b470, 0x3b49c, |
| 0x3b4f0, 0x3b528, |
| 0x3b530, 0x3b548, |
| 0x3b560, 0x3b568, |
| 0x3b570, 0x3b59c, |
| 0x3b5f0, 0x3b638, |
| 0x3b640, 0x3b640, |
| 0x3b648, 0x3b650, |
| 0x3b65c, 0x3b664, |
| 0x3b670, 0x3b6b8, |
| 0x3b6c0, 0x3b6e4, |
| 0x3b6f8, 0x3b738, |
| 0x3b740, 0x3b740, |
| 0x3b748, 0x3b750, |
| 0x3b75c, 0x3b764, |
| 0x3b770, 0x3b7b8, |
| 0x3b7c0, 0x3b7e4, |
| 0x3b7f8, 0x3b7fc, |
| 0x3b814, 0x3b814, |
| 0x3b82c, 0x3b82c, |
| 0x3b880, 0x3b88c, |
| 0x3b8e8, 0x3b8ec, |
| 0x3b900, 0x3b928, |
| 0x3b930, 0x3b948, |
| 0x3b960, 0x3b968, |
| 0x3b970, 0x3b99c, |
| 0x3b9f0, 0x3ba38, |
| 0x3ba40, 0x3ba40, |
| 0x3ba48, 0x3ba50, |
| 0x3ba5c, 0x3ba64, |
| 0x3ba70, 0x3bab8, |
| 0x3bac0, 0x3bae4, |
| 0x3baf8, 0x3bb10, |
| 0x3bb28, 0x3bb28, |
| 0x3bb3c, 0x3bb50, |
| 0x3bbf0, 0x3bc10, |
| 0x3bc28, 0x3bc28, |
| 0x3bc3c, 0x3bc50, |
| 0x3bcf0, 0x3bcfc, |
| 0x3c000, 0x3c030, |
| 0x3c100, 0x3c144, |
| 0x3c190, 0x3c1a0, |
| 0x3c1a8, 0x3c1b8, |
| 0x3c1c4, 0x3c1c8, |
| 0x3c1d0, 0x3c1d0, |
| 0x3c200, 0x3c318, |
| 0x3c400, 0x3c4b4, |
| 0x3c4c0, 0x3c52c, |
| 0x3c540, 0x3c61c, |
| 0x3c800, 0x3c828, |
| 0x3c834, 0x3c834, |
| 0x3c8c0, 0x3c908, |
| 0x3c910, 0x3c9ac, |
| 0x3ca00, 0x3ca14, |
| 0x3ca1c, 0x3ca2c, |
| 0x3ca44, 0x3ca50, |
| 0x3ca74, 0x3ca74, |
| 0x3ca7c, 0x3cafc, |
| 0x3cb08, 0x3cc24, |
| 0x3cd00, 0x3cd00, |
| 0x3cd08, 0x3cd14, |
| 0x3cd1c, 0x3cd20, |
| 0x3cd3c, 0x3cd3c, |
| 0x3cd48, 0x3cd50, |
| 0x3d200, 0x3d20c, |
| 0x3d220, 0x3d220, |
| 0x3d240, 0x3d240, |
| 0x3d600, 0x3d60c, |
| 0x3da00, 0x3da1c, |
| 0x3de00, 0x3de20, |
| 0x3de38, 0x3de3c, |
| 0x3de80, 0x3de80, |
| 0x3de88, 0x3dea8, |
| 0x3deb0, 0x3deb4, |
| 0x3dec8, 0x3ded4, |
| 0x3dfb8, 0x3e004, |
| 0x3e200, 0x3e200, |
| 0x3e208, 0x3e240, |
| 0x3e248, 0x3e280, |
| 0x3e288, 0x3e2c0, |
| 0x3e2c8, 0x3e2fc, |
| 0x3e600, 0x3e630, |
| 0x3ea00, 0x3eabc, |
| 0x3eb00, 0x3eb10, |
| 0x3eb20, 0x3eb30, |
| 0x3eb40, 0x3eb50, |
| 0x3eb60, 0x3eb70, |
| 0x3f000, 0x3f028, |
| 0x3f030, 0x3f048, |
| 0x3f060, 0x3f068, |
| 0x3f070, 0x3f09c, |
| 0x3f0f0, 0x3f128, |
| 0x3f130, 0x3f148, |
| 0x3f160, 0x3f168, |
| 0x3f170, 0x3f19c, |
| 0x3f1f0, 0x3f238, |
| 0x3f240, 0x3f240, |
| 0x3f248, 0x3f250, |
| 0x3f25c, 0x3f264, |
| 0x3f270, 0x3f2b8, |
| 0x3f2c0, 0x3f2e4, |
| 0x3f2f8, 0x3f338, |
| 0x3f340, 0x3f340, |
| 0x3f348, 0x3f350, |
| 0x3f35c, 0x3f364, |
| 0x3f370, 0x3f3b8, |
| 0x3f3c0, 0x3f3e4, |
| 0x3f3f8, 0x3f428, |
| 0x3f430, 0x3f448, |
| 0x3f460, 0x3f468, |
| 0x3f470, 0x3f49c, |
| 0x3f4f0, 0x3f528, |
| 0x3f530, 0x3f548, |
| 0x3f560, 0x3f568, |
| 0x3f570, 0x3f59c, |
| 0x3f5f0, 0x3f638, |
| 0x3f640, 0x3f640, |
| 0x3f648, 0x3f650, |
| 0x3f65c, 0x3f664, |
| 0x3f670, 0x3f6b8, |
| 0x3f6c0, 0x3f6e4, |
| 0x3f6f8, 0x3f738, |
| 0x3f740, 0x3f740, |
| 0x3f748, 0x3f750, |
| 0x3f75c, 0x3f764, |
| 0x3f770, 0x3f7b8, |
| 0x3f7c0, 0x3f7e4, |
| 0x3f7f8, 0x3f7fc, |
| 0x3f814, 0x3f814, |
| 0x3f82c, 0x3f82c, |
| 0x3f880, 0x3f88c, |
| 0x3f8e8, 0x3f8ec, |
| 0x3f900, 0x3f928, |
| 0x3f930, 0x3f948, |
| 0x3f960, 0x3f968, |
| 0x3f970, 0x3f99c, |
| 0x3f9f0, 0x3fa38, |
| 0x3fa40, 0x3fa40, |
| 0x3fa48, 0x3fa50, |
| 0x3fa5c, 0x3fa64, |
| 0x3fa70, 0x3fab8, |
| 0x3fac0, 0x3fae4, |
| 0x3faf8, 0x3fb10, |
| 0x3fb28, 0x3fb28, |
| 0x3fb3c, 0x3fb50, |
| 0x3fbf0, 0x3fc10, |
| 0x3fc28, 0x3fc28, |
| 0x3fc3c, 0x3fc50, |
| 0x3fcf0, 0x3fcfc, |
| 0x40000, 0x4000c, |
| 0x40040, 0x40050, |
| 0x40060, 0x40068, |
| 0x4007c, 0x4008c, |
| 0x40094, 0x400b0, |
| 0x400c0, 0x40144, |
| 0x40180, 0x4018c, |
| 0x40200, 0x40254, |
| 0x40260, 0x40264, |
| 0x40270, 0x40288, |
| 0x40290, 0x40298, |
| 0x402ac, 0x402c8, |
| 0x402d0, 0x402e0, |
| 0x402f0, 0x402f0, |
| 0x40300, 0x4033c, |
| 0x403f8, 0x403fc, |
| 0x41304, 0x413c4, |
| 0x41400, 0x4140c, |
| 0x41414, 0x4141c, |
| 0x41480, 0x414d0, |
| 0x44000, 0x44054, |
| 0x4405c, 0x44078, |
| 0x440c0, 0x44174, |
| 0x44180, 0x441ac, |
| 0x441b4, 0x441b8, |
| 0x441c0, 0x44254, |
| 0x4425c, 0x44278, |
| 0x442c0, 0x44374, |
| 0x44380, 0x443ac, |
| 0x443b4, 0x443b8, |
| 0x443c0, 0x44454, |
| 0x4445c, 0x44478, |
| 0x444c0, 0x44574, |
| 0x44580, 0x445ac, |
| 0x445b4, 0x445b8, |
| 0x445c0, 0x44654, |
| 0x4465c, 0x44678, |
| 0x446c0, 0x44774, |
| 0x44780, 0x447ac, |
| 0x447b4, 0x447b8, |
| 0x447c0, 0x44854, |
| 0x4485c, 0x44878, |
| 0x448c0, 0x44974, |
| 0x44980, 0x449ac, |
| 0x449b4, 0x449b8, |
| 0x449c0, 0x449fc, |
| 0x45000, 0x45004, |
| 0x45010, 0x45030, |
| 0x45040, 0x45060, |
| 0x45068, 0x45068, |
| 0x45080, 0x45084, |
| 0x450a0, 0x450b0, |
| 0x45200, 0x45204, |
| 0x45210, 0x45230, |
| 0x45240, 0x45260, |
| 0x45268, 0x45268, |
| 0x45280, 0x45284, |
| 0x452a0, 0x452b0, |
| 0x460c0, 0x460e4, |
| 0x47000, 0x4703c, |
| 0x47044, 0x4708c, |
| 0x47200, 0x47250, |
| 0x47400, 0x47408, |
| 0x47414, 0x47420, |
| 0x47600, 0x47618, |
| 0x47800, 0x47814, |
| 0x48000, 0x4800c, |
| 0x48040, 0x48050, |
| 0x48060, 0x48068, |
| 0x4807c, 0x4808c, |
| 0x48094, 0x480b0, |
| 0x480c0, 0x48144, |
| 0x48180, 0x4818c, |
| 0x48200, 0x48254, |
| 0x48260, 0x48264, |
| 0x48270, 0x48288, |
| 0x48290, 0x48298, |
| 0x482ac, 0x482c8, |
| 0x482d0, 0x482e0, |
| 0x482f0, 0x482f0, |
| 0x48300, 0x4833c, |
| 0x483f8, 0x483fc, |
| 0x49304, 0x493c4, |
| 0x49400, 0x4940c, |
| 0x49414, 0x4941c, |
| 0x49480, 0x494d0, |
| 0x4c000, 0x4c054, |
| 0x4c05c, 0x4c078, |
| 0x4c0c0, 0x4c174, |
| 0x4c180, 0x4c1ac, |
| 0x4c1b4, 0x4c1b8, |
| 0x4c1c0, 0x4c254, |
| 0x4c25c, 0x4c278, |
| 0x4c2c0, 0x4c374, |
| 0x4c380, 0x4c3ac, |
| 0x4c3b4, 0x4c3b8, |
| 0x4c3c0, 0x4c454, |
| 0x4c45c, 0x4c478, |
| 0x4c4c0, 0x4c574, |
| 0x4c580, 0x4c5ac, |
| 0x4c5b4, 0x4c5b8, |
| 0x4c5c0, 0x4c654, |
| 0x4c65c, 0x4c678, |
| 0x4c6c0, 0x4c774, |
| 0x4c780, 0x4c7ac, |
| 0x4c7b4, 0x4c7b8, |
| 0x4c7c0, 0x4c854, |
| 0x4c85c, 0x4c878, |
| 0x4c8c0, 0x4c974, |
| 0x4c980, 0x4c9ac, |
| 0x4c9b4, 0x4c9b8, |
| 0x4c9c0, 0x4c9fc, |
| 0x4d000, 0x4d004, |
| 0x4d010, 0x4d030, |
| 0x4d040, 0x4d060, |
| 0x4d068, 0x4d068, |
| 0x4d080, 0x4d084, |
| 0x4d0a0, 0x4d0b0, |
| 0x4d200, 0x4d204, |
| 0x4d210, 0x4d230, |
| 0x4d240, 0x4d260, |
| 0x4d268, 0x4d268, |
| 0x4d280, 0x4d284, |
| 0x4d2a0, 0x4d2b0, |
| 0x4e0c0, 0x4e0e4, |
| 0x4f000, 0x4f03c, |
| 0x4f044, 0x4f08c, |
| 0x4f200, 0x4f250, |
| 0x4f400, 0x4f408, |
| 0x4f414, 0x4f420, |
| 0x4f600, 0x4f618, |
| 0x4f800, 0x4f814, |
| 0x50000, 0x50084, |
| 0x50090, 0x500cc, |
| 0x50400, 0x50400, |
| 0x50800, 0x50884, |
| 0x50890, 0x508cc, |
| 0x50c00, 0x50c00, |
| 0x51000, 0x5101c, |
| 0x51300, 0x51308, |
| }; |
| |
| static const unsigned int t6_reg_ranges[] = { |
| 0x1008, 0x101c, |
| 0x1024, 0x10a8, |
| 0x10b4, 0x10f8, |
| 0x1100, 0x1114, |
| 0x111c, 0x112c, |
| 0x1138, 0x113c, |
| 0x1144, 0x114c, |
| 0x1180, 0x1184, |
| 0x1190, 0x1194, |
| 0x11a0, 0x11a4, |
| 0x11b0, 0x11c4, |
| 0x11fc, 0x1274, |
| 0x1280, 0x133c, |
| 0x1800, 0x18fc, |
| 0x3000, 0x302c, |
| 0x3060, 0x30b0, |
| 0x30b8, 0x30d8, |
| 0x30e0, 0x30fc, |
| 0x3140, 0x357c, |
| 0x35a8, 0x35cc, |
| 0x35ec, 0x35ec, |
| 0x3600, 0x5624, |
| 0x56cc, 0x56ec, |
| 0x56f4, 0x5720, |
| 0x5728, 0x575c, |
| 0x580c, 0x5814, |
| 0x5890, 0x589c, |
| 0x58a4, 0x58ac, |
| 0x58b8, 0x58bc, |
| 0x5940, 0x595c, |
| 0x5980, 0x598c, |
| 0x59b0, 0x59c8, |
| 0x59d0, 0x59dc, |
| 0x59fc, 0x5a18, |
| 0x5a60, 0x5a6c, |
| 0x5a80, 0x5a8c, |
| 0x5a94, 0x5a9c, |
| 0x5b94, 0x5bfc, |
| 0x5c10, 0x5e48, |
| 0x5e50, 0x5e94, |
| 0x5ea0, 0x5eb0, |
| 0x5ec0, 0x5ec0, |
| 0x5ec8, 0x5ed0, |
| 0x5ee0, 0x5ee0, |
| 0x5ef0, 0x5ef0, |
| 0x5f00, 0x5f00, |
| 0x6000, 0x6020, |
| 0x6028, 0x6040, |
| 0x6058, 0x609c, |
| 0x60a8, 0x619c, |
| 0x7700, 0x7798, |
| 0x77c0, 0x7880, |
| 0x78cc, 0x78fc, |
| 0x7b00, 0x7b58, |
| 0x7b60, 0x7b84, |
| 0x7b8c, 0x7c54, |
| 0x7d00, 0x7d38, |
| 0x7d40, 0x7d84, |
| 0x7d8c, 0x7ddc, |
| 0x7de4, 0x7e04, |
| 0x7e10, 0x7e1c, |
| 0x7e24, 0x7e38, |
| 0x7e40, 0x7e44, |
| 0x7e4c, 0x7e78, |
| 0x7e80, 0x7edc, |
| 0x7ee8, 0x7efc, |
| 0x8dc0, 0x8de0, |
| 0x8df8, 0x8e04, |
| 0x8e10, 0x8e84, |
| 0x8ea0, 0x8f88, |
| 0x8fb8, 0x9058, |
| 0x9060, 0x9060, |
| 0x9068, 0x90f8, |
| 0x9100, 0x9124, |
| 0x9400, 0x9470, |
| 0x9600, 0x9600, |
| 0x9608, 0x9638, |
| 0x9640, 0x9704, |
| 0x9710, 0x971c, |
| 0x9800, 0x9808, |
| 0x9820, 0x983c, |
| 0x9850, 0x9864, |
| 0x9c00, 0x9c6c, |
| 0x9c80, 0x9cec, |
| 0x9d00, 0x9d6c, |
| 0x9d80, 0x9dec, |
| 0x9e00, 0x9e6c, |
| 0x9e80, 0x9eec, |
| 0x9f00, 0x9f6c, |
| 0x9f80, 0xa020, |
| 0xd004, 0xd03c, |
| 0xd100, 0xd118, |
| 0xd200, 0xd214, |
| 0xd220, 0xd234, |
| 0xd240, 0xd254, |
| 0xd260, 0xd274, |
| 0xd280, 0xd294, |
| 0xd2a0, 0xd2b4, |
| 0xd2c0, 0xd2d4, |
| 0xd2e0, 0xd2f4, |
| 0xd300, 0xd31c, |
| 0xdfc0, 0xdfe0, |
| 0xe000, 0xf008, |
| 0xf010, 0xf018, |
| 0xf020, 0xf028, |
| 0x11000, 0x11014, |
| 0x11048, 0x1106c, |
| 0x11074, 0x11088, |
| 0x11098, 0x11120, |
| 0x1112c, 0x1117c, |
| 0x11190, 0x112e0, |
| 0x11300, 0x1130c, |
| 0x12000, 0x1206c, |
| 0x19040, 0x1906c, |
| 0x19078, 0x19080, |
| 0x1908c, 0x190e8, |
| 0x190f0, 0x190f8, |
| 0x19100, 0x19110, |
| 0x19120, 0x19124, |
| 0x19150, 0x19194, |
| 0x1919c, 0x191b0, |
| 0x191d0, 0x191e8, |
| 0x19238, 0x19290, |
| 0x192a4, 0x192b0, |
| 0x19348, 0x1934c, |
| 0x193f8, 0x19418, |
| 0x19420, 0x19428, |
| 0x19430, 0x19444, |
| 0x1944c, 0x1946c, |
| 0x19474, 0x19474, |
| 0x19490, 0x194cc, |
| 0x194f0, 0x194f8, |
| 0x19c00, 0x19c48, |
| 0x19c50, 0x19c80, |
| 0x19c94, 0x19c98, |
| 0x19ca0, 0x19cbc, |
| 0x19ce4, 0x19ce4, |
| 0x19cf0, 0x19cf8, |
| 0x19d00, 0x19d28, |
| 0x19d50, 0x19d78, |
| 0x19d94, 0x19d98, |
| 0x19da0, 0x19de0, |
| 0x19df0, 0x19e10, |
| 0x19e50, 0x19e6c, |
| 0x19ea0, 0x19ebc, |
| 0x19ec4, 0x19ef4, |
| 0x19f04, 0x19f2c, |
| 0x19f34, 0x19f34, |
| 0x19f40, 0x19f50, |
| 0x19f90, 0x19fac, |
| 0x19fc4, 0x19fc8, |
| 0x19fd0, 0x19fe4, |
| 0x1a000, 0x1a004, |
| 0x1a010, 0x1a06c, |
| 0x1a0b0, 0x1a0e4, |
| 0x1a0ec, 0x1a0f8, |
| 0x1a100, 0x1a108, |
| 0x1a114, 0x1a120, |
| 0x1a128, 0x1a130, |
| 0x1a138, 0x1a138, |
| 0x1a190, 0x1a1c4, |
| 0x1a1fc, 0x1a1fc, |
| 0x1e008, 0x1e00c, |
| 0x1e040, 0x1e044, |
| 0x1e04c, 0x1e04c, |
| 0x1e284, 0x1e290, |
| 0x1e2c0, 0x1e2c0, |
| 0x1e2e0, 0x1e2e0, |
| 0x1e300, 0x1e384, |
| 0x1e3c0, 0x1e3c8, |
| 0x1e408, 0x1e40c, |
| 0x1e440, 0x1e444, |
| 0x1e44c, 0x1e44c, |
| 0x1e684, 0x1e690, |
| 0x1e6c0, 0x1e6c0, |
| 0x1e6e0, 0x1e6e0, |
| 0x1e700, 0x1e784, |
| 0x1e7c0, 0x1e7c8, |
| 0x1e808, 0x1e80c, |
| 0x1e840, 0x1e844, |
| 0x1e84c, 0x1e84c, |
| 0x1ea84, 0x1ea90, |
| 0x1eac0, 0x1eac0, |
| 0x1eae0, 0x1eae0, |
| 0x1eb00, 0x1eb84, |
| 0x1ebc0, 0x1ebc8, |
| 0x1ec08, 0x1ec0c, |
| 0x1ec40, 0x1ec44, |
| 0x1ec4c, 0x1ec4c, |
| 0x1ee84, 0x1ee90, |
| 0x1eec0, 0x1eec0, |
| 0x1eee0, 0x1eee0, |
| 0x1ef00, 0x1ef84, |
| 0x1efc0, 0x1efc8, |
| 0x1f008, 0x1f00c, |
| 0x1f040, 0x1f044, |
| 0x1f04c, 0x1f04c, |
| 0x1f284, 0x1f290, |
| 0x1f2c0, 0x1f2c0, |
| 0x1f2e0, 0x1f2e0, |
| 0x1f300, 0x1f384, |
| 0x1f3c0, 0x1f3c8, |
| 0x1f408, 0x1f40c, |
| 0x1f440, 0x1f444, |
| 0x1f44c, 0x1f44c, |
| 0x1f684, 0x1f690, |
| 0x1f6c0, 0x1f6c0, |
| 0x1f6e0, 0x1f6e0, |
| 0x1f700, 0x1f784, |
| 0x1f7c0, 0x1f7c8, |
| 0x1f808, 0x1f80c, |
| 0x1f840, 0x1f844, |
| 0x1f84c, 0x1f84c, |
| 0x1fa84, 0x1fa90, |
| 0x1fac0, 0x1fac0, |
| 0x1fae0, 0x1fae0, |
| 0x1fb00, 0x1fb84, |
| 0x1fbc0, 0x1fbc8, |
| 0x1fc08, 0x1fc0c, |
| 0x1fc40, 0x1fc44, |
| 0x1fc4c, 0x1fc4c, |
| 0x1fe84, 0x1fe90, |
| 0x1fec0, 0x1fec0, |
| 0x1fee0, 0x1fee0, |
| 0x1ff00, 0x1ff84, |
| 0x1ffc0, 0x1ffc8, |
| 0x30000, 0x30030, |
| 0x30100, 0x30168, |
| 0x30190, 0x301a0, |
| 0x301a8, 0x301b8, |
| 0x301c4, 0x301c8, |
| 0x301d0, 0x301d0, |
| 0x30200, 0x30320, |
| 0x30400, 0x304b4, |
| 0x304c0, 0x3052c, |
| 0x30540, 0x3061c, |
| 0x30800, 0x308a0, |
| 0x308c0, 0x30908, |
| 0x30910, 0x309b8, |
| 0x30a00, 0x30a04, |
| 0x30a0c, 0x30a14, |
| 0x30a1c, 0x30a2c, |
| 0x30a44, 0x30a50, |
| 0x30a74, 0x30a74, |
| 0x30a7c, 0x30afc, |
| 0x30b08, 0x30c24, |
| 0x30d00, 0x30d14, |
| 0x30d1c, 0x30d3c, |
| 0x30d44, 0x30d4c, |
| 0x30d54, 0x30d74, |
| 0x30d7c, 0x30d7c, |
| 0x30de0, 0x30de0, |
| 0x30e00, 0x30ed4, |
| 0x30f00, 0x30fa4, |
| 0x30fc0, 0x30fc4, |
| 0x31000, 0x31004, |
| 0x31080, 0x310fc, |
| 0x31208, 0x31220, |
| 0x3123c, 0x31254, |
| 0x31300, 0x31300, |
| 0x31308, 0x3131c, |
| 0x31338, 0x3133c, |
| 0x31380, 0x31380, |
| 0x31388, 0x313a8, |
| 0x313b4, 0x313b4, |
| 0x31400, 0x31420, |
| 0x31438, 0x3143c, |
| 0x31480, 0x31480, |
| 0x314a8, 0x314a8, |
| 0x314b0, 0x314b4, |
| 0x314c8, 0x314d4, |
| 0x31a40, 0x31a4c, |
| 0x31af0, 0x31b20, |
| 0x31b38, 0x31b3c, |
| 0x31b80, 0x31b80, |
| 0x31ba8, 0x31ba8, |
| 0x31bb0, 0x31bb4, |
| 0x31bc8, 0x31bd4, |
| 0x32140, 0x3218c, |
| 0x321f0, 0x321f4, |
| 0x32200, 0x32200, |
| 0x32218, 0x32218, |
| 0x32400, 0x32400, |
| 0x32408, 0x3241c, |
| 0x32618, 0x32620, |
| 0x32664, 0x32664, |
| 0x326a8, 0x326a8, |
| 0x326ec, 0x326ec, |
| 0x32a00, 0x32abc, |
| 0x32b00, 0x32b18, |
| 0x32b20, 0x32b38, |
| 0x32b40, 0x32b58, |
| 0x32b60, 0x32b78, |
| 0x32c00, 0x32c00, |
| 0x32c08, 0x32c3c, |
| 0x33000, 0x3302c, |
| 0x33034, 0x33050, |
| 0x33058, 0x33058, |
| 0x33060, 0x3308c, |
| 0x3309c, 0x330ac, |
| 0x330c0, 0x330c0, |
| 0x330c8, 0x330d0, |
| 0x330d8, 0x330e0, |
| 0x330ec, 0x3312c, |
| 0x33134, 0x33150, |
| 0x33158, 0x33158, |
| 0x33160, 0x3318c, |
| 0x3319c, 0x331ac, |
| 0x331c0, 0x331c0, |
| 0x331c8, 0x331d0, |
| 0x331d8, 0x331e0, |
| 0x331ec, 0x33290, |
| 0x33298, 0x332c4, |
| 0x332e4, 0x33390, |
| 0x33398, 0x333c4, |
| 0x333e4, 0x3342c, |
| 0x33434, 0x33450, |
| 0x33458, 0x33458, |
| 0x33460, 0x3348c, |
| 0x3349c, 0x334ac, |
| 0x334c0, 0x334c0, |
| 0x334c8, 0x334d0, |
| 0x334d8, 0x334e0, |
| 0x334ec, 0x3352c, |
| 0x33534, 0x33550, |
| 0x33558, 0x33558, |
| 0x33560, 0x3358c, |
| 0x3359c, 0x335ac, |
| 0x335c0, 0x335c0, |
| 0x335c8, 0x335d0, |
| 0x335d8, 0x335e0, |
| 0x335ec, 0x33690, |
| 0x33698, 0x336c4, |
| 0x336e4, 0x33790, |
| 0x33798, 0x337c4, |
| 0x337e4, 0x337fc, |
| 0x33814, 0x33814, |
| 0x33854, 0x33868, |
| 0x33880, 0x3388c, |
| 0x338c0, 0x338d0, |
| 0x338e8, 0x338ec, |
| 0x33900, 0x3392c, |
| 0x33934, 0x33950, |
| 0x33958, 0x33958, |
| 0x33960, 0x3398c, |
| 0x3399c, 0x339ac, |
| 0x339c0, 0x339c0, |
| 0x339c8, 0x339d0, |
| 0x339d8, 0x339e0, |
| 0x339ec, 0x33a90, |
| 0x33a98, 0x33ac4, |
| 0x33ae4, 0x33b10, |
| 0x33b24, 0x33b28, |
| 0x33b38, 0x33b50, |
| 0x33bf0, 0x33c10, |
| 0x33c24, 0x33c28, |
| 0x33c38, 0x33c50, |
| 0x33cf0, 0x33cfc, |
| 0x34000, 0x34030, |
| 0x34100, 0x34168, |
| 0x34190, 0x341a0, |
| 0x341a8, 0x341b8, |
| 0x341c4, 0x341c8, |
| 0x341d0, 0x341d0, |
| 0x34200, 0x34320, |
| 0x34400, 0x344b4, |
| 0x344c0, 0x3452c, |
| 0x34540, 0x3461c, |
| 0x34800, 0x348a0, |
| 0x348c0, 0x34908, |
| 0x34910, 0x349b8, |
| 0x34a00, 0x34a04, |
| 0x34a0c, 0x34a14, |
| 0x34a1c, 0x34a2c, |
| 0x34a44, 0x34a50, |
| 0x34a74, 0x34a74, |
| 0x34a7c, 0x34afc, |
| 0x34b08, 0x34c24, |
| 0x34d00, 0x34d14, |
| 0x34d1c, 0x34d3c, |
| 0x34d44, 0x34d4c, |
| 0x34d54, 0x34d74, |
| 0x34d7c, 0x34d7c, |
| 0x34de0, 0x34de0, |
| 0x34e00, 0x34ed4, |
| 0x34f00, 0x34fa4, |
| 0x34fc0, 0x34fc4, |
| 0x35000, 0x35004, |
| 0x35080, 0x350fc, |
| 0x35208, 0x35220, |
| 0x3523c, 0x35254, |
| 0x35300, 0x35300, |
| 0x35308, 0x3531c, |
| 0x35338, 0x3533c, |
| 0x35380, 0x35380, |
| 0x35388, 0x353a8, |
| 0x353b4, 0x353b4, |
| 0x35400, 0x35420, |
| 0x35438, 0x3543c, |
| 0x35480, 0x35480, |
| 0x354a8, 0x354a8, |
| 0x354b0, 0x354b4, |
|