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code.illumos.org / illumos-gate / 77b62fe435d195b5a58f123e6c5ec9c9dffdc877 / . / usr / src / uts / common / io / qede / 579xx / drivers / ecore / ecore_dbg_fw_funcs.c
blob: 62c6a7ada4db3fc3cfc2a207f8ec356fffa82618 [file] [log] [blame]
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, v.1, (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://opensource.org/licenses/CDDL-1.0.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2014-2017 Cavium, Inc.
* The contents of this file are subject to the terms of the Common Development
* and Distribution License, v.1, (the "License").
* You may not use this file except in compliance with the License.
* You can obtain a copy of the License at available
* at http://opensource.org/licenses/CDDL-1.0
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "bcm_osal.h"
#include "ecore.h"
#include "ecore_hw.h"
#include "ecore_mcp.h"
#include "spad_layout.h"
#include "nvm_map.h"
#include "reg_addr.h"
#include "ecore_hsi_common.h"
#include "ecore_hsi_debug_tools.h"
#include "mcp_public.h"
#include "nvm_map.h"
#ifndef USE_DBG_BIN_FILE
#include "ecore_dbg_values.h"
#endif
#include "ecore_dbg_fw_funcs.h"
/* Memory groups enum */
enum mem_groups {
MEM_GROUP_PXP_MEM,
MEM_GROUP_DMAE_MEM,
MEM_GROUP_CM_MEM,
MEM_GROUP_QM_MEM,
MEM_GROUP_TM_MEM,
MEM_GROUP_BRB_RAM,
MEM_GROUP_BRB_MEM,
MEM_GROUP_PRS_MEM,
MEM_GROUP_SDM_MEM,
MEM_GROUP_IOR,
MEM_GROUP_RAM,
MEM_GROUP_BTB_RAM,
MEM_GROUP_RDIF_CTX,
MEM_GROUP_TDIF_CTX,
MEM_GROUP_CFC_MEM,
MEM_GROUP_CONN_CFC_MEM,
MEM_GROUP_TASK_CFC_MEM,
MEM_GROUP_CAU_PI,
MEM_GROUP_CAU_MEM,
MEM_GROUP_PXP_ILT,
MEM_GROUP_PBUF,
MEM_GROUP_MULD_MEM,
MEM_GROUP_BTB_MEM,
MEM_GROUP_IGU_MEM,
MEM_GROUP_IGU_MSIX,
MEM_GROUP_CAU_SB,
MEM_GROUP_BMB_RAM,
MEM_GROUP_BMB_MEM,
MEM_GROUPS_NUM
};
/* Memory groups names */
static const char* s_mem_group_names[] = {
"PXP_MEM",
"DMAE_MEM",
"CM_MEM",
"QM_MEM",
"TM_MEM",
"BRB_RAM",
"BRB_MEM",
"PRS_MEM",
"SDM_MEM",
"IOR",
"RAM",
"BTB_RAM",
"RDIF_CTX",
"TDIF_CTX",
"CFC_MEM",
"CONN_CFC_MEM",
"TASK_CFC_MEM",
"CAU_PI",
"CAU_MEM",
"PXP_ILT",
"PBUF",
"MULD_MEM",
"BTB_MEM",
"IGU_MEM",
"IGU_MSIX",
"CAU_SB",
"BMB_RAM",
"BMB_MEM",
};
/* Idle check conditions */
#ifndef __PREVENT_COND_ARR__
static u32 cond5(const u32 *r, const u32 *imm) {
return (((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]));
}
static u32 cond7(const u32 *r, const u32 *imm) {
return (((r[0] >> imm[0]) & imm[1]) != imm[2]);
}
static u32 cond14(const u32 *r, const u32 *imm) {
return ((r[0] != imm[0]) && (((r[1] >> imm[1]) & imm[2]) == imm[3]));
}
static u32 cond6(const u32 *r, const u32 *imm) {
return ((r[0] & imm[0]) != imm[1]);
}
static u32 cond9(const u32 *r, const u32 *imm) {
return ((r[0] & imm[0]) >> imm[1]) != (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5]));
}
static u32 cond10(const u32 *r, const u32 *imm) {
return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]);
}
static u32 cond4(const u32 *r, const u32 *imm) {
return ((r[0] & ~imm[0]) != imm[1]);
}
static u32 cond0(const u32 *r, const u32 *imm) {
return ((r[0] & ~r[1]) != imm[0]);
}
static u32 cond1(const u32 *r, const u32 *imm) {
return (r[0] != imm[0]);
}
static u32 cond11(const u32 *r, const u32 *imm) {
return (r[0] != r[1] && r[2] == imm[0]);
}
static u32 cond12(const u32 *r, const u32 *imm) {
return (r[0] != r[1] && r[2] > imm[0]);
}
static u32 cond3(const u32 *r, const u32 *imm) {
return (r[0] != r[1]);
}
static u32 cond13(const u32 *r, const u32 *imm) {
return (r[0] & imm[0]);
}
static u32 cond8(const u32 *r, const u32 *imm) {
return (r[0] < (r[1] - imm[0]));
}
static u32 cond2(const u32 *r, const u32 *imm) {
return (r[0] > imm[0]);
}
/* Array of Idle Check conditions */
static u32 (*cond_arr[])(const u32 *r, const u32 *imm) = {
cond0,
cond1,
cond2,
cond3,
cond4,
cond5,
cond6,
cond7,
cond8,
cond9,
cond10,
cond11,
cond12,
cond13,
cond14,
};
#endif /* __PREVENT_COND_ARR__ */
/******************************* Data Types **********************************/
enum platform_ids {
PLATFORM_ASIC,
PLATFORM_EMUL_FULL,
PLATFORM_EMUL_REDUCED,
PLATFORM_FPGA,
MAX_PLATFORM_IDS
};
struct chip_platform_defs {
u8 num_ports;
u8 num_pfs;
u8 num_vfs;
};
/* Chip constant definitions */
struct chip_defs {
const char *name;
struct chip_platform_defs per_platform[MAX_PLATFORM_IDS];
};
/* Platform constant definitions */
struct platform_defs {
const char *name;
u32 delay_factor;
};
/* Storm constant definitions.
* Addresses are in bytes, sizes are in quad-regs.
*/
struct storm_defs {
char letter;
enum block_id block_id;
enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
bool has_vfc;
u32 sem_fast_mem_addr;
u32 sem_frame_mode_addr;
u32 sem_slow_enable_addr;
u32 sem_slow_mode_addr;
u32 sem_slow_mode1_conf_addr;
u32 sem_sync_dbg_empty_addr;
u32 sem_slow_dbg_empty_addr;
u32 cm_ctx_wr_addr;
u32 cm_conn_ag_ctx_lid_size;
u32 cm_conn_ag_ctx_rd_addr;
u32 cm_conn_st_ctx_lid_size;
u32 cm_conn_st_ctx_rd_addr;
u32 cm_task_ag_ctx_lid_size;
u32 cm_task_ag_ctx_rd_addr;
u32 cm_task_st_ctx_lid_size;
u32 cm_task_st_ctx_rd_addr;
};
/* Block constant definitions */
struct block_defs {
const char *name;
bool has_dbg_bus[MAX_CHIP_IDS];
bool associated_to_storm;
/* Valid only if associated_to_storm is true */
u32 storm_id;
enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
u32 dbg_select_addr;
u32 dbg_enable_addr;
u32 dbg_shift_addr;
u32 dbg_force_valid_addr;
u32 dbg_force_frame_addr;
bool has_reset_bit;
/* If true, block is taken out of reset before dump */
bool unreset;
enum dbg_reset_regs reset_reg;
/* Bit offset in reset register */
u8 reset_bit_offset;
};
/* Reset register definitions */
struct reset_reg_defs {
u32 addr;
u32 unreset_val;
bool exists[MAX_CHIP_IDS];
};
/* Debug Bus Constraint operation constant definitions */
struct dbg_bus_constraint_op_defs {
u8 hw_op_val;
bool is_cyclic;
};
/* Storm Mode definitions */
struct storm_mode_defs {
const char *name;
bool is_fast_dbg;
u8 id_in_hw;
};
struct grc_param_defs {
u32 default_val[MAX_CHIP_IDS];
u32 min;
u32 max;
bool is_preset;
u32 exclude_all_preset_val;
u32 crash_preset_val;
};
/* address is in 128b units. Width is in bits. */
struct rss_mem_defs {
const char *mem_name;
const char *type_name;
u32 addr;
u32 num_entries[MAX_CHIP_IDS];
u32 entry_width[MAX_CHIP_IDS];
};
struct vfc_ram_defs {
const char *mem_name;
const char *type_name;
u32 base_row;
u32 num_rows;
};
struct big_ram_defs {
const char *instance_name;
enum mem_groups mem_group_id;
enum mem_groups ram_mem_group_id;
enum dbg_grc_params grc_param;
u32 addr_reg_addr;
u32 data_reg_addr;
u32 num_of_blocks[MAX_CHIP_IDS];
};
struct phy_defs {
const char *phy_name;
/* PHY base GRC address */
u32 base_addr;
/* Relative address of indirect TBUS address register (bits 0..7) */
u32 tbus_addr_lo_addr;
/* Relative address of indirect TBUS address register (bits 8..10) */
u32 tbus_addr_hi_addr;
/* Relative address of indirect TBUS data register (bits 0..7) */
u32 tbus_data_lo_addr;
/* Relative address of indirect TBUS data register (bits 8..11) */
u32 tbus_data_hi_addr;
};
/******************************** Constants **********************************/
#define MAX_LCIDS 320
#define MAX_LTIDS 320
#define NUM_IOR_SETS 2
#define IORS_PER_SET 176
#define IOR_SET_OFFSET(set_id) ((set_id) * 256)
#define BYTES_IN_DWORD sizeof(u32)
/* Cyclic right */
#define SHR(val, val_width, amount) (((val) | ((val) << (val_width))) >> (amount)) & ((1 << (val_width)) - 1)
/* In the macros below, size and offset are specified in bits */
#define CEIL_DWORDS(size) DIV_ROUND_UP(size, 32)
#define FIELD_BIT_OFFSET(type, field) type##_##field##_##OFFSET
#define FIELD_BIT_SIZE(type, field) type##_##field##_##SIZE
#define FIELD_DWORD_OFFSET(type, field) (int)(FIELD_BIT_OFFSET(type, field) / 32)
#define FIELD_DWORD_SHIFT(type, field) (FIELD_BIT_OFFSET(type, field) % 32)
#define FIELD_BIT_MASK(type, field) (((1 << FIELD_BIT_SIZE(type, field)) - 1) << FIELD_DWORD_SHIFT(type, field))
#define SET_VAR_FIELD(var, type, field, val) var[FIELD_DWORD_OFFSET(type, field)] &= (~FIELD_BIT_MASK(type, field)); var[FIELD_DWORD_OFFSET(type, field)] |= (val) << FIELD_DWORD_SHIFT(type, field)
#define ARR_REG_WR(dev, ptt, addr, arr, arr_size) for (i = 0; i < (arr_size); i++) ecore_wr(dev, ptt, addr, (arr)[i])
#define ARR_REG_RD(dev, ptt, addr, arr, arr_size) for (i = 0; i < (arr_size); i++) (arr)[i] = ecore_rd(dev, ptt, addr)
#define CHECK_ARR_SIZE(arr, size) OSAL_BUILD_BUG_ON(!(OSAL_ARRAY_SIZE(arr) == size))
#ifndef DWORDS_TO_BYTES
#define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD)
#endif
#ifndef BYTES_TO_DWORDS
#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
#endif
/* extra lines include a signature line + optional latency events line */
#ifndef NUM_DBG_LINES
#define NUM_EXTRA_DBG_LINES(block_desc) (1 + (block_desc->has_latency_events ? 1 : 0))
#define NUM_DBG_LINES(block_desc) (block_desc->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
#endif
#define RAM_LINES_TO_DWORDS(lines) ((lines) * 2)
#define RAM_LINES_TO_BYTES(lines) DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines))
#define REG_DUMP_LEN_SHIFT 24
#define MEM_DUMP_ENTRY_SIZE_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem))
#define IDLE_CHK_RULE_SIZE_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule))
#define IDLE_CHK_RESULT_HDR_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr))
#define IDLE_CHK_RESULT_REG_HDR_DWORDS BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr))
#define IDLE_CHK_MAX_ENTRIES_SIZE 32
/* The sizes and offsets below are specified in bits */
#define VFC_CAM_CMD_STRUCT_SIZE 64
#define VFC_CAM_CMD_ROW_OFFSET 48
#define VFC_CAM_CMD_ROW_SIZE 9
#define VFC_CAM_ADDR_STRUCT_SIZE 16
#define VFC_CAM_ADDR_OP_OFFSET 0
#define VFC_CAM_ADDR_OP_SIZE 4
#define VFC_CAM_RESP_STRUCT_SIZE 256
#define VFC_RAM_ADDR_STRUCT_SIZE 16
#define VFC_RAM_ADDR_OP_OFFSET 0
#define VFC_RAM_ADDR_OP_SIZE 2
#define VFC_RAM_ADDR_ROW_OFFSET 2
#define VFC_RAM_ADDR_ROW_SIZE 10
#define VFC_RAM_RESP_STRUCT_SIZE 256
#define VFC_CAM_CMD_DWORDS CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE)
#define VFC_CAM_ADDR_DWORDS CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE)
#define VFC_CAM_RESP_DWORDS CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE)
#define VFC_RAM_CMD_DWORDS VFC_CAM_CMD_DWORDS
#define VFC_RAM_ADDR_DWORDS CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE)
#define VFC_RAM_RESP_DWORDS CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE)
#define NUM_VFC_RAM_TYPES 4
#define VFC_CAM_NUM_ROWS 512
#define VFC_OPCODE_CAM_RD 14
#define VFC_OPCODE_RAM_RD 0
#define NUM_RSS_MEM_TYPES 5
#define NUM_BIG_RAM_TYPES 3
#define BIG_RAM_BLOCK_SIZE_BYTES 128
#define BIG_RAM_BLOCK_SIZE_DWORDS BYTES_TO_DWORDS(BIG_RAM_BLOCK_SIZE_BYTES)
#define NUM_PHY_TBUS_ADDRESSES 2048
#define PHY_DUMP_SIZE_DWORDS (NUM_PHY_TBUS_ADDRESSES / 2)
#define SEM_FAST_MODE6_SRC_ENABLE 0x10
#define SEM_FAST_MODE6_SRC_DISABLE 0x3f
#define SEM_SLOW_MODE1_DATA_ENABLE 0x1
#define VALUES_PER_CYCLE 4
#define MAX_CYCLE_VALUES_MASK ((1 << VALUES_PER_CYCLE) - 1)
#define MAX_DWORDS_PER_CYCLE 8
#define HW_ID_BITS 3
#define NUM_CALENDAR_SLOTS 16
#define MAX_TRIGGER_STATES 3
#define TRIGGER_SETS_PER_STATE 2
#define MAX_CONSTRAINTS 4
#define SEM_FILTER_CID_EN_MASK 0x008
#define SEM_FILTER_EID_MASK_EN_MASK 0x010
#define SEM_FILTER_EID_RANGE_EN_MASK 0x110
#define CHUNK_SIZE_IN_DWORDS 64
#define CHUNK_SIZE_IN_BYTES DWORDS_TO_BYTES(CHUNK_SIZE_IN_DWORDS)
#define INT_BUF_NUM_OF_LINES 192
#define INT_BUF_LINE_SIZE_IN_DWORDS 16
#define INT_BUF_SIZE_IN_DWORDS (INT_BUF_NUM_OF_LINES * INT_BUF_LINE_SIZE_IN_DWORDS)
#define INT_BUF_SIZE_IN_CHUNKS (INT_BUF_SIZE_IN_DWORDS / CHUNK_SIZE_IN_DWORDS)
#define PCI_BUF_LINE_SIZE_IN_DWORDS 8
#define PCI_BUF_LINE_SIZE_IN_BYTES DWORDS_TO_BYTES(PCI_BUF_LINE_SIZE_IN_DWORDS)
#define TARGET_EN_MASK_PCI 0x3
#define TARGET_EN_MASK_NIG 0x4
#define PCI_REQ_CREDIT 1
#define PCI_PHYS_ADDR_TYPE 0
#define OPAQUE_FID(pci_func) ((pci_func << 4) | 0xff00)
#define RESET_REG_UNRESET_OFFSET 4
#define PCI_PKT_SIZE_IN_CHUNKS 1
#define PCI_PKT_SIZE_IN_BYTES (PCI_PKT_SIZE_IN_CHUNKS * CHUNK_SIZE_IN_BYTES)
#define NIG_PKT_SIZE_IN_CHUNKS 4
#define FLUSH_DELAY_MS 500
#define STALL_DELAY_MS 500
#define SRC_MAC_ADDR_LO16 0x0a0b
#define SRC_MAC_ADDR_HI32 0x0c0d0e0f
#define ETH_TYPE 0x1000
#define STATIC_DEBUG_LINE_DWORDS 9
#define NUM_COMMON_GLOBAL_PARAMS 8
#define FW_IMG_KUKU 0
#define FW_IMG_MAIN 1
#define FW_IMG_L2B 2
#ifndef REG_FIFO_ELEMENT_DWORDS
#define REG_FIFO_ELEMENT_DWORDS 2
#endif
#define REG_FIFO_DEPTH_ELEMENTS 32
#define REG_FIFO_DEPTH_DWORDS (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)
#ifndef IGU_FIFO_ELEMENT_DWORDS
#define IGU_FIFO_ELEMENT_DWORDS 4
#endif
#define IGU_FIFO_DEPTH_ELEMENTS 64
#define IGU_FIFO_DEPTH_DWORDS (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)
#define SEMI_SYNC_FIFO_POLLING_DELAY_MS 5
#define SEMI_SYNC_FIFO_POLLING_COUNT 20
#ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS
#define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2
#endif
#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20
#define PROTECTION_OVERRIDE_DEPTH_DWORDS (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * PROTECTION_OVERRIDE_ELEMENT_DWORDS)
#define MCP_SPAD_TRACE_OFFSIZE_ADDR (MCP_REG_SCRATCH + OFFSETOF(struct static_init, sections[SPAD_SECTION_TRACE]))
#define EMPTY_FW_VERSION_STR "???_???_???_???"
#define EMPTY_FW_IMAGE_STR "???????????????"
/***************************** Constant Arrays *******************************/
struct dbg_array {
const u32 *ptr;
u32 size_in_dwords;
};
/* Debug arrays */
#ifdef USE_DBG_BIN_FILE
static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { { OSAL_NULL } };
#else
static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = {
/* BIN_BUF_DBG_MODE_TREE */
{ (u32*)dbg_modes_tree_buf, OSAL_ARRAY_SIZE(dbg_modes_tree_buf)},
/* BIN_BUF_DBG_DUMP_REG */
{ dump_reg, OSAL_ARRAY_SIZE(dump_reg) },
/* BIN_BUF_DBG_DUMP_MEM */
{ dump_mem, OSAL_ARRAY_SIZE(dump_mem) },
/* BIN_BUF_DBG_IDLE_CHK_REGS */
{ idle_chk_regs, OSAL_ARRAY_SIZE(idle_chk_regs) },
/* BIN_BUF_DBG_IDLE_CHK_IMMS */
{ idle_chk_imms, OSAL_ARRAY_SIZE(idle_chk_imms) },
/* BIN_BUF_DBG_IDLE_CHK_RULES */
{ idle_chk_rules, OSAL_ARRAY_SIZE(idle_chk_rules) },
/* BIN_BUF_DBG_IDLE_CHK_PARSING_DATA */
{ OSAL_NULL, 0 },
/* BIN_BUF_DBG_ATTN_BLOCKS */
{ attn_block, OSAL_ARRAY_SIZE(attn_block) },
/* BIN_BUF_DBG_ATTN_REGSS */
{ attn_reg, OSAL_ARRAY_SIZE(attn_reg) },
/* BIN_BUF_DBG_ATTN_INDEXES */
{ OSAL_NULL, 0 },
/* BIN_BUF_DBG_ATTN_NAME_OFFSETS */
{ OSAL_NULL, 0 },
/* BIN_BUF_DBG_BUS_BLOCKS */
{ dbg_bus_blocks, OSAL_ARRAY_SIZE(dbg_bus_blocks) },
/* BIN_BUF_DBG_BUS_LINES */
{ dbg_bus_lines, OSAL_ARRAY_SIZE(dbg_bus_lines) },
/* BIN_BUF_DBG_BUS_BLOCKS_USER_DATA */
{ OSAL_NULL, 0 },
/* BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS */
{ OSAL_NULL, 0 },
/* BIN_BUF_DBG_PARSING_STRINGS */
{ OSAL_NULL, 0 }
};
#endif
/* Chip constant definitions array */
static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = {
{ "bb",
/* ASIC */
{ { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
/* EMUL_FULL */
{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
/* EMUL_REDUCED */
{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB },
/* FPGA */
{ MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB } } },
{ "ah",
/* ASIC */
{ { MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
/* EMUL_FULL */
{ MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
/* EMUL_REDUCED */
{ MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2 },
/* FPGA */
{ MAX_NUM_PORTS_K2, 8, MAX_NUM_VFS_K2 } } }
};
/* Storm constant definitions array */
static struct storm_defs s_storm_defs[] = {
/* Tstorm */
{ 'T', BLOCK_TSEM,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT }, true,
TSEM_REG_FAST_MEMORY,
TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
TCM_REG_CTX_RBC_ACCS,
4, TCM_REG_AGG_CON_CTX,
16, TCM_REG_SM_CON_CTX,
2, TCM_REG_AGG_TASK_CTX,
4, TCM_REG_SM_TASK_CTX },
/* Mstorm */
{ 'M', BLOCK_MSEM,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM }, false,
MSEM_REG_FAST_MEMORY,
MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2,
MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2,
MCM_REG_CTX_RBC_ACCS,
1, MCM_REG_AGG_CON_CTX,
10, MCM_REG_SM_CON_CTX,
2, MCM_REG_AGG_TASK_CTX,
7, MCM_REG_SM_TASK_CTX },
/* Ustorm */
{ 'U', BLOCK_USEM,
{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU }, false,
USEM_REG_FAST_MEMORY,
USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2,
USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2,
UCM_REG_CTX_RBC_ACCS,
2, UCM_REG_AGG_CON_CTX,
13, UCM_REG_SM_CON_CTX,
3, UCM_REG_AGG_TASK_CTX,
3, UCM_REG_SM_TASK_CTX },
/* Xstorm */
{ 'X', BLOCK_XSEM,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX }, false,
XSEM_REG_FAST_MEMORY,
XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2,
XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2,
XCM_REG_CTX_RBC_ACCS,
9, XCM_REG_AGG_CON_CTX,
15, XCM_REG_SM_CON_CTX,
0, 0,
0, 0 },
/* Ystorm */
{ 'Y', BLOCK_YSEM,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY }, false,
YSEM_REG_FAST_MEMORY,
YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2,
YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
YCM_REG_CTX_RBC_ACCS,
2, YCM_REG_AGG_CON_CTX,
3, YCM_REG_SM_CON_CTX,
2, YCM_REG_AGG_TASK_CTX,
12, YCM_REG_SM_TASK_CTX },
/* Pstorm */
{ 'P', BLOCK_PSEM,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS }, true,
PSEM_REG_FAST_MEMORY,
PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2,
PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2,
PCM_REG_CTX_RBC_ACCS,
0, 0,
10, PCM_REG_SM_CON_CTX,
0, 0,
0, 0 }
};
/* Block definitions array */
static struct block_defs block_grc_defs = {
"grc", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN },
GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE,
GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID,
GRC_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_UA, 1 };
static struct block_defs block_miscs_defs = {
"miscs", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_misc_defs = {
"misc", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_dbu_defs = {
"dbu", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_pglue_b_defs = {
"pglue_b", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH },
PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE,
PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID,
PGLUE_B_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISCS_PL_HV, 1 };
static struct block_defs block_cnig_defs = {
"cnig", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW },
CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
CNIG_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 0 };
static struct block_defs block_cpmu_defs = {
"cpmu", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_HV, 8 };
static struct block_defs block_ncsi_defs = {
"ncsi", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ },
NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE,
NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID,
NCSI_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISCS_PL_HV, 5 };
static struct block_defs block_opte_defs = {
"opte", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_HV, 4 };
static struct block_defs block_bmb_defs = {
"bmb", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB },
BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE,
BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID,
BMB_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISCS_PL_UA, 7 };
static struct block_defs block_pcie_defs = {
"pcie", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH },
PCIE_REG_DBG_COMMON_SELECT_K2_E5, PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
PCIE_REG_DBG_COMMON_SHIFT_K2_E5, PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_mcp_defs = {
"mcp", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_mcp2_defs = {
"mcp2", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ },
MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE,
MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID,
MCP2_REG_DBG_FORCE_FRAME,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_pswhst_defs = {
"pswhst", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE,
PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID,
PSWHST_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_HV, 0 };
static struct block_defs block_pswhst2_defs = {
"pswhst2", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE,
PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID,
PSWHST2_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_HV, 0 };
static struct block_defs block_pswrd_defs = {
"pswrd", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE,
PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID,
PSWRD_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_HV, 2 };
static struct block_defs block_pswrd2_defs = {
"pswrd2", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE,
PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID,
PSWRD2_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_HV, 2 };
static struct block_defs block_pswwr_defs = {
"pswwr", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE,
PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID,
PSWWR_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_HV, 3 };
static struct block_defs block_pswwr2_defs = {
"pswwr2", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISC_PL_HV, 3 };
static struct block_defs block_pswrq_defs = {
"pswrq", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE,
PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID,
PSWRQ_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_HV, 1 };
static struct block_defs block_pswrq2_defs = {
"pswrq2", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE,
PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID,
PSWRQ2_REG_DBG_FORCE_FRAME,
true, false, DBG_RESET_REG_MISC_PL_HV, 1 };
static struct block_defs block_pglcs_defs = {
"pglcs", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH },
PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 2 };
static struct block_defs block_ptu_defs ={
"ptu", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE,
PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID,
PTU_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20 };
static struct block_defs block_dmae_defs = {
"dmae", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE,
DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID,
DMAE_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28 };
static struct block_defs block_tcm_defs = {
"tcm", { true, true }, true, DBG_TSTORM_ID,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE,
TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID,
TCM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5 };
static struct block_defs block_mcm_defs = {
"mcm", { true, true }, true, DBG_MSTORM_ID,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE,
MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID,
MCM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3 };
static struct block_defs block_ucm_defs = {
"ucm", { true, true }, true, DBG_USTORM_ID,
{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE,
UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID,
UCM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8 };
static struct block_defs block_xcm_defs = {
"xcm", { true, true }, true, DBG_XSTORM_ID,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE,
XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID,
XCM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19 };
static struct block_defs block_ycm_defs = {
"ycm", { true, true }, true, DBG_YSTORM_ID,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE,
YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID,
YCM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5 };
static struct block_defs block_pcm_defs = {
"pcm", { true, true }, true, DBG_PSTORM_ID,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE,
PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID,
PCM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4 };
static struct block_defs block_qm_defs = {
"qm", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ },
QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE,
QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID,
QM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16 };
static struct block_defs block_tm_defs = {
"tm", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE,
TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID,
TM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17 };
static struct block_defs block_dorq_defs = {
"dorq", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE,
DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID,
DORQ_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18 };
static struct block_defs block_brb_defs = {
"brb", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR },
BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE,
BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID,
BRB_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0 };
static struct block_defs block_src_defs = {
"src", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE,
SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID,
SRC_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2 };
static struct block_defs block_prs_defs = {
"prs", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR },
PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE,
PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID,
PRS_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1 };
static struct block_defs block_tsdm_defs = {
"tsdm", { true, true }, true, DBG_TSTORM_ID,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE,
TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID,
TSDM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3 };
static struct block_defs block_msdm_defs = {
"msdm", { true, true }, true, DBG_MSTORM_ID,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE,
MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID,
MSDM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6 };
static struct block_defs block_usdm_defs = {
"usdm", { true, true }, true, DBG_USTORM_ID,
{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE,
USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID,
USDM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7
};
static struct block_defs block_xsdm_defs = {
"xsdm", { true, true }, true, DBG_XSTORM_ID,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE,
XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID,
XSDM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20 };
static struct block_defs block_ysdm_defs = {
"ysdm", { true, true }, true, DBG_YSTORM_ID,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE,
YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID,
YSDM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8 };
static struct block_defs block_psdm_defs = {
"psdm", { true, true }, true, DBG_PSTORM_ID,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE,
PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID,
PSDM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7 };
static struct block_defs block_tsem_defs = {
"tsem", { true, true }, true, DBG_TSTORM_ID,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE,
TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID,
TSEM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4 };
static struct block_defs block_msem_defs = {
"msem", { true, true }, true, DBG_MSTORM_ID,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE,
MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID,
MSEM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9 };
static struct block_defs block_usem_defs = {
"usem", { true, true }, true, DBG_USTORM_ID,
{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE,
USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID,
USEM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9 };
static struct block_defs block_xsem_defs = {
"xsem", { true, true }, true, DBG_XSTORM_ID,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE,
XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID,
XSEM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21 };
static struct block_defs block_ysem_defs = {
"ysem", { true, true }, true, DBG_YSTORM_ID,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY },
YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE,
YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID,
YSEM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11 };
static struct block_defs block_psem_defs = {
"psem", { true, true }, true, DBG_PSTORM_ID,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE,
PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID,
PSEM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10 };
static struct block_defs block_rss_defs = {
"rss", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT },
RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE,
RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID,
RSS_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18 };
static struct block_defs block_tmld_defs = {
"tmld", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE,
TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID,
TMLD_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13 };
static struct block_defs block_muld_defs = {
"muld", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE,
MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID,
MULD_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14 };
static struct block_defs block_yuld_defs = {
"yuld", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU },
YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2,
YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2,
YULD_REG_DBG_FORCE_FRAME_BB_K2,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 15 };
static struct block_defs block_xyld_defs = {
"xyld", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX },
XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE,
XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID,
XYLD_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12 };
static struct block_defs block_prm_defs = {
"prm", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE,
PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID,
PRM_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21 };
static struct block_defs block_pbf_pb1_defs = {
"pbf_pb1", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV },
PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE,
PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID,
PBF_PB1_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 11 };
static struct block_defs block_pbf_pb2_defs = {
"pbf_pb2", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV },
PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE,
PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID,
PBF_PB2_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 12 };
static struct block_defs block_rpb_defs = {
"rpb", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE,
RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID,
RPB_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13 };
static struct block_defs block_btb_defs = {
"btb", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV },
BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE,
BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID,
BTB_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10 };
static struct block_defs block_pbf_defs = {
"pbf", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV },
PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE,
PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID,
PBF_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15 };
static struct block_defs block_rdif_defs = {
"rdif", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM },
RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE,
RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID,
RDIF_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16 };
static struct block_defs block_tdif_defs = {
"tdif", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS },
TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE,
TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID,
TDIF_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17 };
static struct block_defs block_cdu_defs = {
"cdu", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE,
CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID,
CDU_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23 };
static struct block_defs block_ccfc_defs = {
"ccfc", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE,
CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID,
CCFC_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24 };
static struct block_defs block_tcfc_defs = {
"tcfc", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF },
TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE,
TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID,
TCFC_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25 };
static struct block_defs block_igu_defs = {
"igu", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE,
IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID,
IGU_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27 };
static struct block_defs block_cau_defs = {
"cau", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP },
CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE,
CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID,
CAU_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19 };
static struct block_defs block_umac_defs = {
"umac", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ },
UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
UMAC_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 6 };
static struct block_defs block_xmac_defs = {
"xmac", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_dbg_defs = {
"dbg", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3 };
static struct block_defs block_nig_defs = {
"nig", { true, true }, false, 0,
{ DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN },
NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE,
NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID,
NIG_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0 };
static struct block_defs block_wol_defs = {
"wol", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ },
WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
WOL_REG_DBG_FORCE_FRAME_K2_E5,
true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7 };
static struct block_defs block_bmbn_defs = {
"bmbn", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB },
BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
BMBN_REG_DBG_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_ipc_defs = {
"ipc", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_UA, 8 };
static struct block_defs block_nwm_defs = {
"nwm", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW },
NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
NWM_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0 };
static struct block_defs block_nws_defs = {
"nws", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW },
NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
NWS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 12 };
static struct block_defs block_ms_defs = {
"ms", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ },
MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
MS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 13 };
static struct block_defs block_phy_pcie_defs = {
"phy_pcie", { false, true }, false, 0,
{ MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH },
PCIE_REG_DBG_COMMON_SELECT_K2_E5, PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
PCIE_REG_DBG_COMMON_SHIFT_K2_E5, PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_led_defs = {
"led", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_HV, 14 };
static struct block_defs block_avs_wrap_defs = {
"avs_wrap", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_UA, 11 };
static struct block_defs block_rgfs_defs = {
"rgfs", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_rgsrc_defs = {
"rgsrc", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_tgfs_defs = {
"tgfs", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_tgsrc_defs = {
"tgsrc", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_ptld_defs = {
"ptld", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_ypld_defs = {
"ypld", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_misc_aeu_defs = {
"misc_aeu", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs block_bar0_map_defs = {
"bar0_map", { false, false }, false, 0,
{ MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS },
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0 };
static struct block_defs* s_block_defs[MAX_BLOCK_ID] = {
&block_grc_defs,
&block_miscs_defs,
&block_misc_defs,
&block_dbu_defs,
&block_pglue_b_defs,
&block_cnig_defs,
&block_cpmu_defs,
&block_ncsi_defs,
&block_opte_defs,
&block_bmb_defs,
&block_pcie_defs,
&block_mcp_defs,
&block_mcp2_defs,
&block_pswhst_defs,
&block_pswhst2_defs,
&block_pswrd_defs,
&block_pswrd2_defs,
&block_pswwr_defs,
&block_pswwr2_defs,
&block_pswrq_defs,
&block_pswrq2_defs,
&block_pglcs_defs,
&block_dmae_defs,
&block_ptu_defs,
&block_tcm_defs,
&block_mcm_defs,
&block_ucm_defs,
&block_xcm_defs,
&block_ycm_defs,
&block_pcm_defs,
&block_qm_defs,
&block_tm_defs,
&block_dorq_defs,
&block_brb_defs,
&block_src_defs,
&block_prs_defs,
&block_tsdm_defs,
&block_msdm_defs,
&block_usdm_defs,
&block_xsdm_defs,
&block_ysdm_defs,
&block_psdm_defs,
&block_tsem_defs,
&block_msem_defs,
&block_usem_defs,
&block_xsem_defs,
&block_ysem_defs,
&block_psem_defs,
&block_rss_defs,
&block_tmld_defs,
&block_muld_defs,
&block_yuld_defs,
&block_xyld_defs,
&block_ptld_defs,
&block_ypld_defs,
&block_prm_defs,
&block_pbf_pb1_defs,
&block_pbf_pb2_defs,
&block_rpb_defs,
&block_btb_defs,
&block_pbf_defs,
&block_rdif_defs,
&block_tdif_defs,
&block_cdu_defs,
&block_ccfc_defs,
&block_tcfc_defs,
&block_igu_defs,
&block_cau_defs,
&block_rgfs_defs,
&block_rgsrc_defs,
&block_tgfs_defs,
&block_tgsrc_defs,
&block_umac_defs,
&block_xmac_defs,
&block_dbg_defs,
&block_nig_defs,
&block_wol_defs,
&block_bmbn_defs,
&block_ipc_defs,
&block_nwm_defs,
&block_nws_defs,
&block_ms_defs,
&block_phy_pcie_defs,
&block_led_defs,
&block_avs_wrap_defs,
&block_misc_aeu_defs,
&block_bar0_map_defs,
};
/* Constraint operation types */
static struct dbg_bus_constraint_op_defs s_constraint_op_defs[] = {
/* DBG_BUS_CONSTRAINT_OP_EQ */
{ 0, false },
/* DBG_BUS_CONSTRAINT_OP_NE */
{ 5, false },
/* DBG_BUS_CONSTRAINT_OP_LT */
{ 1, false },
/* DBG_BUS_CONSTRAINT_OP_LTC */
{ 1, true },
/* DBG_BUS_CONSTRAINT_OP_LE */
{ 2, false },
/* DBG_BUS_CONSTRAINT_OP_LEC */
{ 2, true },
/* DBG_BUS_CONSTRAINT_OP_GT */
{ 4, false },
/* DBG_BUS_CONSTRAINT_OP_GTC */
{ 4, true },
/* DBG_BUS_CONSTRAINT_OP_GE */
{ 3, false },
/* DBG_BUS_CONSTRAINT_OP_GEC */
{ 3, true }
};
static const char* s_dbg_target_names[] = {
/* DBG_BUS_TARGET_ID_INT_BUF */
"int-buf",
/* DBG_BUS_TARGET_ID_NIG */
"nw",
/* DBG_BUS_TARGET_ID_PCI */
"pci-buf"
};
static struct storm_mode_defs s_storm_mode_defs[] = {
/* DBG_BUS_STORM_MODE_PRINTF */
{ "printf", true, 0 },
/* DBG_BUS_STORM_MODE_PRAM_ADDR */
{ "pram_addr", true, 1 },
/* DBG_BUS_STORM_MODE_DRA_RW */
{ "dra_rw", true, 2 },
/* DBG_BUS_STORM_MODE_DRA_W */
{ "dra_w", true, 3 },
/* DBG_BUS_STORM_MODE_LD_ST_ADDR */
{ "ld_st_addr", true, 4 },
/* DBG_BUS_STORM_MODE_DRA_FSM */
{ "dra_fsm", true, 5 },
/* DBG_BUS_STORM_MODE_RH */
{ "rh", true, 6 },
/* DBG_BUS_STORM_MODE_FOC */
{ "foc", false, 1 },
/* DBG_BUS_STORM_MODE_EXT_STORE */
{ "ext_store", false, 3 }
};
static struct platform_defs s_platform_defs[] = {
/* PLATFORM_ASIC */
{ "asic", 1 },
/* PLATFORM_EMUL_FULL */
{ "emul_full", 2000 },
/* PLATFORM_EMUL_REDUCED */
{ "emul_reduced", 2000 },
/* PLATFORM_FPGA */
{ "fpga", 200 }
};
static struct grc_param_defs s_grc_param_defs[] = {
/* DBG_GRC_PARAM_DUMP_TSTORM */
{ { 1, 1 }, 0, 1, false, 1, 1 },
/* DBG_GRC_PARAM_DUMP_MSTORM */
{ { 1, 1 }, 0, 1, false, 1, 1 },
/* DBG_GRC_PARAM_DUMP_USTORM */
{ { 1, 1 }, 0, 1, false, 1, 1 },
/* DBG_GRC_PARAM_DUMP_XSTORM */
{ { 1, 1 }, 0, 1, false, 1, 1 },
/* DBG_GRC_PARAM_DUMP_YSTORM */
{ { 1, 1 }, 0, 1, false, 1, 1 },
/* DBG_GRC_PARAM_DUMP_PSTORM */
{ { 1, 1 }, 0, 1, false, 1, 1 },
/* DBG_GRC_PARAM_DUMP_REGS */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_RAM */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_PBUF */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_IOR */
{ { 0, 0 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_VFC */
{ { 0, 0 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_CM_CTX */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_ILT */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_RSS */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_CAU */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_QM */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_MCP */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_RESERVED */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_CFC */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_IGU */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_BRB */
{ { 0, 0 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_BTB */
{ { 0, 0 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_BMB */
{ { 0, 0 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_NIG */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_MULD */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_PRS */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_DMAE */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_TM */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_SDM */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_DIF */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_STATIC */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_UNSTALL */
{ { 0, 0 }, 0, 1, false, 0, 0 },
/* DBG_GRC_PARAM_NUM_LCIDS */
{ { MAX_LCIDS, MAX_LCIDS }, 1, MAX_LCIDS, false, MAX_LCIDS, MAX_LCIDS },
/* DBG_GRC_PARAM_NUM_LTIDS */
{ { MAX_LTIDS, MAX_LTIDS }, 1, MAX_LTIDS, false, MAX_LTIDS, MAX_LTIDS },
/* DBG_GRC_PARAM_EXCLUDE_ALL */
{ { 0, 0 }, 0, 1, true, 0, 0 },
/* DBG_GRC_PARAM_CRASH */
{ { 0, 0 }, 0, 1, true, 0, 0 },
/* DBG_GRC_PARAM_PARITY_SAFE */
{ { 0, 0 }, 0, 1, false, 1, 0 },
/* DBG_GRC_PARAM_DUMP_CM */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_DUMP_PHY */
{ { 1, 1 }, 0, 1, false, 0, 1 },
/* DBG_GRC_PARAM_NO_MCP */
{ { 0, 0 }, 0, 1, false, 0, 0 },
/* DBG_GRC_PARAM_NO_FW_VER */
{ { 0, 0 }, 0, 1, false, 0, 0 }
};
static struct rss_mem_defs s_rss_mem_defs[] = {
{ "rss_mem_cid", "rss_cid", 0,
{ 256, 320 },
{ 32, 32 } },
{ "rss_mem_key_msb", "rss_key", 1024,
{ 128, 208 },
{ 256, 256 } },
{ "rss_mem_key_lsb", "rss_key", 2048,
{ 128, 208 },
{ 64, 64 } },
{ "rss_mem_info", "rss_info", 3072,
{ 128, 208 },
{ 16, 16 } },
{ "rss_mem_ind", "rss_ind", 4096,
{ 16384, 26624 },
{ 16, 16 } }
};
static struct vfc_ram_defs s_vfc_ram_defs[] = {
{ "vfc_ram_tt1", "vfc_ram", 0, 512 },
{ "vfc_ram_mtt2", "vfc_ram", 512, 128 },
{ "vfc_ram_stt2", "vfc_ram", 640, 32 },
{ "vfc_ram_ro_vect", "vfc_ram", 672, 32 }
};
static struct big_ram_defs s_big_ram_defs[] = {
{ "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB, BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
{ 4800, 5632 } },
{ "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB, BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
{ 2880, 3680 } },
{ "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB, BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
{ 1152, 1152 } }
};
static struct reset_reg_defs s_reset_regs_defs[] = {
/* DBG_RESET_REG_MISCS_PL_UA */
{ MISCS_REG_RESET_PL_UA, 0x0, { true, true } },
/* DBG_RESET_REG_MISCS_PL_HV */
{ MISCS_REG_RESET_PL_HV, 0x0, { true, true } },
/* DBG_RESET_REG_MISCS_PL_HV_2 */
{ MISCS_REG_RESET_PL_HV_2_K2_E5, 0x0, { false, true } },
/* DBG_RESET_REG_MISC_PL_UA */
{ MISC_REG_RESET_PL_UA, 0x0, { true, true } },
/* DBG_RESET_REG_MISC_PL_HV */
{ MISC_REG_RESET_PL_HV, 0x0, { true, true } },
/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */
{ MISC_REG_RESET_PL_PDA_VMAIN_1, 0x4404040, { true, true } },
/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */
{ MISC_REG_RESET_PL_PDA_VMAIN_2, 0x7c00007, { true, true } },
/* DBG_RESET_REG_MISC_PL_PDA_VAUX */
{ MISC_REG_RESET_PL_PDA_VAUX, 0x2, { true, true } },
};
static struct phy_defs s_phy_defs[] = {
{ "nw_phy", NWS_REG_NWS_CMU_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5, PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 },
{ "sgmii_phy", MS_REG_MS_CMU_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 },
{ "pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 },
{ "pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 },
};
/* The order of indexes that should be applied to a PCI buffer line */
static const u8 s_pci_buf_line_ind[PCI_BUF_LINE_SIZE_IN_DWORDS] = { 1, 0, 3, 2, 5, 4, 7, 6 };
/******************************** Variables **********************************/
/* The version of the calling app */
static u32 s_app_ver;
/**************************** Private Functions ******************************/
static void ecore_static_asserts(void)
{
CHECK_ARR_SIZE(s_dbg_arrays, MAX_BIN_DBG_BUFFER_TYPE);
CHECK_ARR_SIZE(s_big_ram_defs, NUM_BIG_RAM_TYPES);
CHECK_ARR_SIZE(s_vfc_ram_defs, NUM_VFC_RAM_TYPES);
CHECK_ARR_SIZE(s_rss_mem_defs, NUM_RSS_MEM_TYPES);
CHECK_ARR_SIZE(s_chip_defs, MAX_CHIP_IDS);
CHECK_ARR_SIZE(s_platform_defs, MAX_PLATFORM_IDS);
CHECK_ARR_SIZE(s_storm_defs, MAX_DBG_STORMS);
CHECK_ARR_SIZE(s_constraint_op_defs, MAX_DBG_BUS_CONSTRAINT_OPS);
CHECK_ARR_SIZE(s_dbg_target_names, MAX_DBG_BUS_TARGETS);
CHECK_ARR_SIZE(s_storm_mode_defs, MAX_DBG_BUS_STORM_MODES);
CHECK_ARR_SIZE(s_grc_param_defs, MAX_DBG_GRC_PARAMS);
CHECK_ARR_SIZE(s_reset_regs_defs, MAX_DBG_RESET_REGS);
}
/* Reads and returns a single dword from the specified unaligned buffer. */
static u32 ecore_read_unaligned_dword(u8 *buf)
{
u32 dword;
OSAL_MEMCPY((u8*)&dword, buf, sizeof(dword));
return dword;
}
/* Returns the difference in bytes between the specified physical addresses.
* Assumes that the first address is bigger then the second, and that the
* difference is a 32-bit value.
*/
static u32 ecore_phys_addr_diff(struct dbg_bus_mem_addr *a,
struct dbg_bus_mem_addr *b)
{
return a->hi == b->hi ? a->lo - b->lo : b->lo - a->lo;
}
/* Sets the value of the specified GRC param */
static void ecore_grc_set_param(struct ecore_hwfn *p_hwfn,
enum dbg_grc_params grc_param,
u32 val)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
dev_data->grc.param_val[grc_param] = val;
}
/* Returns the value of the specified GRC param */
static u32 ecore_grc_get_param(struct ecore_hwfn *p_hwfn,
enum dbg_grc_params grc_param)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
return dev_data->grc.param_val[grc_param];
}
/* Initializes the GRC parameters */
static void ecore_dbg_grc_init_params(struct ecore_hwfn *p_hwfn)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
if (!dev_data->grc.params_initialized) {
ecore_dbg_grc_set_params_default(p_hwfn);
dev_data->grc.params_initialized = 1;
}
}
/* Initializes debug data for the specified device */
static enum dbg_status ecore_dbg_dev_init(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
if (dev_data->initialized)
return DBG_STATUS_OK;
if (!s_app_ver)
return DBG_STATUS_APP_VERSION_NOT_SET;
if (ECORE_IS_K2(p_hwfn->p_dev)) {
dev_data->chip_id = CHIP_K2;
dev_data->mode_enable[MODE_K2] = 1;
}
else if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
dev_data->chip_id = CHIP_BB;
dev_data->mode_enable[MODE_BB] = 1;
}
else {
return DBG_STATUS_UNKNOWN_CHIP;
}
#ifdef ASIC_ONLY
dev_data->platform_id = PLATFORM_ASIC;
dev_data->mode_enable[MODE_ASIC] = 1;
#else
if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
dev_data->platform_id = PLATFORM_ASIC;
dev_data->mode_enable[MODE_ASIC] = 1;
}
else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
if (ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED) & 0x20000000) {
dev_data->platform_id = PLATFORM_EMUL_FULL;
dev_data->mode_enable[MODE_EMUL_FULL] = 1;
}
else {
dev_data->platform_id = PLATFORM_EMUL_REDUCED;
dev_data->mode_enable[MODE_EMUL_REDUCED] = 1;
}
}
else if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
dev_data->platform_id = PLATFORM_FPGA;
dev_data->mode_enable[MODE_FPGA] = 1;
}
else {
return DBG_STATUS_UNKNOWN_CHIP;
}
#endif
/* Initializes the GRC parameters */
ecore_dbg_grc_init_params(p_hwfn);
dev_data->initialized = true;
return DBG_STATUS_OK;
}
static struct dbg_bus_block* get_dbg_bus_block_desc(struct ecore_hwfn *p_hwfn,
enum block_id block_id)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
return (struct dbg_bus_block*)&dbg_bus_blocks[block_id * MAX_CHIP_IDS + dev_data->chip_id];
}
/* Returns OSAL_NULL for signature line, latency line and non-existing lines */
static struct dbg_bus_line* get_dbg_bus_line_desc(struct ecore_hwfn *p_hwfn,
enum block_id block_id)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
struct dbg_bus_block_data *block_bus;
struct dbg_bus_block *block_desc;
block_bus = &dev_data->bus.blocks[block_id];
block_desc = get_dbg_bus_block_desc(p_hwfn, block_id);
if (!block_bus->line_num ||
(block_bus->line_num == 1 && block_desc->has_latency_events) ||
block_bus->line_num >= NUM_DBG_LINES(block_desc))
return OSAL_NULL;
return (struct dbg_bus_line*)&dbg_bus_lines[block_desc->lines_offset + block_bus->line_num - NUM_EXTRA_DBG_LINES(block_desc)];
}
/* Reads the FW info structure for the specified Storm from the chip,
* and writes it to the specified fw_info pointer.
*/
static void ecore_read_fw_info(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 storm_id,
struct fw_info *fw_info)
{
struct storm_defs *storm = &s_storm_defs[storm_id];
struct fw_info_location fw_info_location;
u32 addr, i, *dest;
OSAL_MEMSET(&fw_info_location, 0, sizeof(fw_info_location));
OSAL_MEMSET(fw_info, 0, sizeof(*fw_info));
/* Read first the address that points to fw_info location.
* The address is located in the last line of the Storm RAM.
*/
addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM + DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE) - sizeof(fw_info_location);
dest = (u32*)&fw_info_location;
for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location)); i++, addr += BYTES_IN_DWORD)
dest[i] = ecore_rd(p_hwfn, p_ptt, addr);
/* Read FW version info from Storm RAM */
if (fw_info_location.size > 0 && fw_info_location.size <= sizeof(*fw_info)) {
addr = fw_info_location.grc_addr;
dest = (u32*)fw_info;
for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size); i++, addr += BYTES_IN_DWORD)
dest[i] = ecore_rd(p_hwfn, p_ptt, addr);
}
}
/* Dumps the specified string to the specified buffer.
* Returns the dumped size in bytes.
*/
static u32 ecore_dump_str(char *dump_buf,
bool dump,
const char *str)
{
if (dump)
OSAL_STRCPY(dump_buf, str);
return (u32)OSAL_STRLEN(str) + 1;
}
/* Dumps zeros to align the specified buffer to dwords.
* Returns the dumped size in bytes.
*/
static u32 ecore_dump_align(char *dump_buf,
bool dump,
u32 byte_offset)
{
u8 offset_in_dword, align_size;
offset_in_dword = (u8)(byte_offset & 0x3);
align_size = offset_in_dword ? BYTES_IN_DWORD - offset_in_dword : 0;
if (dump && align_size)
OSAL_MEMSET(dump_buf, 0, align_size);
return align_size;
}
/* Writes the specified string param to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_dump_str_param(u32 *dump_buf,
bool dump,
const char *param_name,
const char *param_val)
{
char *char_buf = (char*)dump_buf;
u32 offset = 0;
/* Dump param name */
offset += ecore_dump_str(char_buf + offset, dump, param_name);
/* Indicate a string param value */
if (dump)
*(char_buf + offset) = 1;
offset++;
/* Dump param value */
offset += ecore_dump_str(char_buf + offset, dump, param_val);
/* Align buffer to next dword */
offset += ecore_dump_align(char_buf + offset, dump, offset);
return BYTES_TO_DWORDS(offset);
}
/* Writes the specified numeric param to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_dump_num_param(u32 *dump_buf,
bool dump,
const char *param_name,
u32 param_val)
{
char *char_buf = (char*)dump_buf;
u32 offset = 0;
/* Dump param name */
offset += ecore_dump_str(char_buf + offset, dump, param_name);
/* Indicate a numeric param value */
if (dump)
*(char_buf + offset) = 0;
offset++;
/* Align buffer to next dword */
offset += ecore_dump_align(char_buf + offset, dump, offset);
/* Dump param value (and change offset from bytes to dwords) */
offset = BYTES_TO_DWORDS(offset);
if (dump)
*(dump_buf + offset) = param_val;
offset++;
return offset;
}
/* Reads the FW version and writes it as a param to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_dump_fw_ver_param(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *dump_buf,
bool dump)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
char fw_ver_str[16] = EMPTY_FW_VERSION_STR;
char fw_img_str[16] = EMPTY_FW_IMAGE_STR;
struct fw_info fw_info = { { 0 }, { 0 } };
u32 offset = 0;
if (dump && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) {
/* Read FW image/version from PRAM in a non-reset SEMI */
bool found = false;
u8 storm_id;
for (storm_id = 0; storm_id < MAX_DBG_STORMS && !found; storm_id++) {
struct storm_defs *storm = &s_storm_defs[storm_id];
/* Read FW version/image */
if (dev_data->block_in_reset[storm->block_id])
continue;
/* Read FW info for the current Storm */
ecore_read_fw_info(p_hwfn, p_ptt, storm_id, &fw_info);
/* Create FW version/image strings */
if (OSAL_SNPRINTF(fw_ver_str, sizeof(fw_ver_str), "%d_%d_%d_%d", fw_info.ver.num.major, fw_info.ver.num.minor, fw_info.ver.num.rev, fw_info.ver.num.eng) < 0)
DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid FW version string\n");
switch (fw_info.ver.image_id) {
case FW_IMG_KUKU: OSAL_STRCPY(fw_img_str, "kuku"); break;
case FW_IMG_MAIN: OSAL_STRCPY(fw_img_str, "main"); break;
case FW_IMG_L2B: OSAL_STRCPY(fw_img_str, "l2b"); break;
default: OSAL_STRCPY(fw_img_str, "unknown"); break;
}
found = true;
}
}
/* Dump FW version, image and timestamp */
offset += ecore_dump_str_param(dump_buf + offset, dump, "fw-version", fw_ver_str);
offset += ecore_dump_str_param(dump_buf + offset, dump, "fw-image", fw_img_str);
offset += ecore_dump_num_param(dump_buf + offset, dump, "fw-timestamp", fw_info.ver.timestamp);
return offset;
}
/* Reads the MFW version and writes it as a param to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_dump_mfw_ver_param(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *dump_buf,
bool dump)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
char mfw_ver_str[16] = EMPTY_FW_VERSION_STR;
bool is_emul;
is_emul = dev_data->platform_id == PLATFORM_EMUL_FULL || dev_data->platform_id == PLATFORM_EMUL_REDUCED;
if (dump && !is_emul && !ecore_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) {
u32 public_data_addr, global_section_offsize_addr, global_section_offsize, global_section_addr, mfw_ver;
/* Find MCP public data GRC address. Needs to be ORed with
* MCP_REG_SCRATCH due to a HW bug.
*/
public_data_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR) | MCP_REG_SCRATCH;
/* Find MCP public global section offset */
global_section_offsize_addr = public_data_addr + OFFSETOF(struct mcp_public_data, sections) + sizeof(offsize_t) * PUBLIC_GLOBAL;
global_section_offsize = ecore_rd(p_hwfn, p_ptt, global_section_offsize_addr);
global_section_addr = MCP_REG_SCRATCH + (global_section_offsize & OFFSIZE_OFFSET_MASK) * 4;
/* Read MFW version from MCP public global section */
mfw_ver = ecore_rd(p_hwfn, p_ptt, global_section_addr + OFFSETOF(struct public_global, mfw_ver));
/* Dump MFW version param */
if (OSAL_SNPRINTF(mfw_ver_str, sizeof(mfw_ver_str), "%d_%d_%d_%d", (u8)(mfw_ver >> 24), (u8)(mfw_ver >> 16), (u8)(mfw_ver >> 8), (u8)mfw_ver) < 0)
DP_NOTICE(p_hwfn, true, "Unexpected debug error: invalid MFW version string\n");
}
return ecore_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str);
}
/* Writes a section header to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_dump_section_hdr(u32 *dump_buf,
bool dump,
const char *name,
u32 num_params)
{
return ecore_dump_num_param(dump_buf, dump, name, num_params);
}
/* Writes the common global params to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_dump_common_global_params(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *dump_buf,
bool dump,
u8 num_specific_global_params)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u32 offset = 0;
u8 num_params;
/* Dump global params section header */
num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params;
offset += ecore_dump_section_hdr(dump_buf + offset, dump, "global_params", num_params);
/* Store params */
offset += ecore_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump);
offset += ecore_dump_mfw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump);
offset += ecore_dump_num_param(dump_buf + offset, dump, "tools-version", TOOLS_VERSION);
offset += ecore_dump_str_param(dump_buf + offset, dump, "chip", s_chip_defs[dev_data->chip_id].name);
offset += ecore_dump_str_param(dump_buf + offset, dump, "platform", s_platform_defs[dev_data->platform_id].name);
offset += ecore_dump_num_param(dump_buf + offset, dump, "pci-func", p_hwfn->abs_pf_id);
return offset;
}
/* Writes the "last" section (including CRC) to the specified buffer at the
* given offset. Returns the dumped size in dwords.
*/
static u32 ecore_dump_last_section(struct ecore_hwfn *p_hwfn,
u32 *dump_buf,
u32 offset,
bool dump)
{
u32 start_offset = offset;
/* Dump CRC section header */
offset += ecore_dump_section_hdr(dump_buf + offset, dump, "last", 0);
/* Calculate CRC32 and add it to the dword after the "last" section */
if (dump)
*(dump_buf + offset) = ~OSAL_CRC32(0xffffffff, (u8*)dump_buf, DWORDS_TO_BYTES(offset));
offset++;
return offset - start_offset;
}
/* Update blocks reset state */
static void ecore_update_blocks_reset_state(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
u32 i;
/* Read reset registers */
for (i = 0; i < MAX_DBG_RESET_REGS; i++)
if (s_reset_regs_defs[i].exists[dev_data->chip_id])
reg_val[i] = ecore_rd(p_hwfn, p_ptt, s_reset_regs_defs[i].addr);
/* Check if blocks are in reset */
for (i = 0; i < MAX_BLOCK_ID; i++) {
struct block_defs *block = s_block_defs[i];
dev_data->block_in_reset[i] = block->has_reset_bit && !(reg_val[block->reset_reg] & (1 << block->reset_bit_offset));
}
}
/* Enable / disable the Debug block */
static void ecore_bus_enable_dbg_block(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
bool enable)
{
ecore_wr(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON, enable ? 1 : 0);
}
/* Resets the Debug block */
static void ecore_bus_reset_dbg_block(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val;
struct block_defs *dbg_block = s_block_defs[BLOCK_DBG];
dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr;
old_reset_reg_val = ecore_rd(p_hwfn, p_ptt, dbg_reset_reg_addr);
new_reset_reg_val = old_reset_reg_val & ~(1 << dbg_block->reset_bit_offset);
ecore_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val);
ecore_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val);
}
static void ecore_bus_set_framing_mode(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
enum dbg_bus_frame_modes mode)
{
ecore_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode);
}
/* Enable / disable Debug Bus clients according to the specified mask
* (1 = enable, 0 = disable).
*/
static void ecore_bus_enable_clients(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 client_mask)
{
ecore_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask);
}
/* Enables the specified Storm for Debug Bus. Assumes a valid Storm ID. */
static void ecore_bus_enable_storm(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
enum dbg_storms storm_id,
enum dbg_bus_filter_types filter_type)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u32 base_addr, sem_filter_params = filter_type;
struct dbg_bus_storm_data *storm_bus;
struct storm_mode_defs *storm_mode;
struct storm_defs *storm;
storm = &s_storm_defs[storm_id];
storm_bus = &dev_data->bus.storms[storm_id];
storm_mode = &s_storm_mode_defs[storm_bus->mode];
base_addr = storm->sem_fast_mem_addr;
/* Config SEM */
if (storm_mode->is_fast_dbg) {
/* Enable fast debug */
ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST);
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_MODE, storm_mode->id_in_hw);
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_ACTIVE, 1);
/* Enable all messages except STORE. Must be done after
* enabling SEM_FAST_REG_DEBUG_ACTIVE, otherwise messages will
* be dropped after the SEMI sync fifo is filled.
*/
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DBG_MODE6_SRC_DISABLE, SEM_FAST_MODE6_SRC_ENABLE);
}
else {
/* Ensable slow debug */
ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST);
ecore_wr(p_hwfn, p_ptt, storm->sem_slow_enable_addr, 1);
ecore_wr(p_hwfn, p_ptt, storm->sem_slow_mode_addr, storm_mode->id_in_hw);
ecore_wr(p_hwfn, p_ptt, storm->sem_slow_mode1_conf_addr, SEM_SLOW_MODE1_DATA_ENABLE);
}
/* Config SEM cid filter */
if (storm_bus->cid_filter_en) {
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_FILTER_CID, storm_bus->cid);
sem_filter_params |= SEM_FILTER_CID_EN_MASK;
}
/* Config SEM eid filter */
if (storm_bus->eid_filter_en) {
const union dbg_bus_storm_eid_params *eid_filter = &storm_bus->eid_filter_params;
if (storm_bus->eid_range_not_mask) {
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_RANGE_STRT, eid_filter->range.min);
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_RANGE_END, eid_filter->range.max);
sem_filter_params |= SEM_FILTER_EID_RANGE_EN_MASK;
}
else {
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_FILTER_EVENT_ID, eid_filter->mask.val);
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_EVENT_ID_MASK, ~eid_filter->mask.mask);
sem_filter_params |= SEM_FILTER_EID_MASK_EN_MASK;
}
}
/* Config accumulaed SEM filter parameters (if any) */
if (sem_filter_params)
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_RECORD_FILTER_ENABLE, sem_filter_params);
}
/* Disables Debug Bus block inputs */
static enum dbg_status ecore_bus_disable_inputs(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
bool empty_semi_fifos)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u8 storm_id, num_fifos_to_empty = MAX_DBG_STORMS;
bool is_fifo_empty[MAX_DBG_STORMS] = { false };
u32 block_id;
/* Disable messages output in all Storms */
for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
struct storm_defs *storm = &s_storm_defs[storm_id];
if (!dev_data->block_in_reset[storm->block_id])
ecore_wr(p_hwfn, p_ptt, storm->sem_fast_mem_addr + SEM_FAST_REG_DBG_MODE6_SRC_DISABLE, SEM_FAST_MODE6_SRC_DISABLE);
}
/* Try to empty the SEMI sync fifo. Must be done after messages output
* were disabled in all Storms (i.e. SEM_FAST_REG_DBG_MODE6_SRC_DISABLE
* was set to all 1's.
*/
while (num_fifos_to_empty) {
for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
struct storm_defs *storm = &s_storm_defs[storm_id];
if (is_fifo_empty[storm_id])
continue;
/* Check if sync fifo got empty */
if (dev_data->block_in_reset[storm->block_id] || ecore_rd(p_hwfn, p_ptt, storm->sem_sync_dbg_empty_addr)) {
is_fifo_empty[storm_id] = true;
num_fifos_to_empty--;
}
}
/* Check if need to continue polling */
if (num_fifos_to_empty) {
u32 polling_ms = SEMI_SYNC_FIFO_POLLING_DELAY_MS * s_platform_defs[dev_data->platform_id].delay_factor;
u32 polling_count = 0;
if (empty_semi_fifos && polling_count < SEMI_SYNC_FIFO_POLLING_COUNT) {
OSAL_MSLEEP(polling_ms);
polling_count++;
}
else {
DP_NOTICE(p_hwfn, false, "Warning: failed to empty the SEMI sync FIFO. It means that the last few messages from the SEMI could not be sent to the DBG block. This can happen when the DBG block is blocked (e.g. due to a PCI problem).\n");
break;
}
}
}
/* Disable debug in all Storms */
for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
struct storm_defs *storm = &s_storm_defs[storm_id];
u32 base_addr = storm->sem_fast_mem_addr;
if (dev_data->block_in_reset[storm->block_id])
continue;
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_DEBUG_ACTIVE, 0);
ecore_wr(p_hwfn, p_ptt, base_addr + SEM_FAST_REG_RECORD_FILTER_ENABLE, DBG_BUS_FILTER_TYPE_OFF);
ecore_wr(p_hwfn, p_ptt, storm->sem_frame_mode_addr, DBG_BUS_FRAME_MODE_4HW_0ST);
ecore_wr(p_hwfn, p_ptt, storm->sem_slow_enable_addr, 0);
}
/* Disable all clients */
ecore_bus_enable_clients(p_hwfn, p_ptt, 0);
/* Disable all blocks */
for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
struct block_defs *block = s_block_defs[block_id];
if (block->has_dbg_bus[dev_data->chip_id] && !dev_data->block_in_reset[block_id])
ecore_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0);
}
/* Disable timestamp */
ecore_wr(p_hwfn, p_ptt, DBG_REG_TIMESTAMP_VALID_EN, 0);
/* Disable filters and triggers */
ecore_wr(p_hwfn, p_ptt, DBG_REG_FILTER_ENABLE, DBG_BUS_FILTER_TYPE_OFF);
ecore_wr(p_hwfn, p_ptt, DBG_REG_TRIGGER_ENABLE, 0);
return DBG_STATUS_OK;
}
/* Sets a Debug Bus trigger/filter constraint */
static void ecore_bus_set_constraint(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
bool is_filter,
u8 constraint_id,
u8 hw_op_val,
u32 data_val,
u32 data_mask,
u8 frame_bit,
u8 frame_mask,
u16 dword_offset,
u16 range,
u8 cyclic_bit,
u8 must_bit)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u32 reg_offset = constraint_id * BYTES_IN_DWORD;
u8 curr_trigger_state;
/* For trigger only - set register offset according to state */
if (!is_filter) {
curr_trigger_state = dev_data->bus.next_trigger_state - 1;
reg_offset += curr_trigger_state * TRIGGER_SETS_PER_STATE * MAX_CONSTRAINTS * BYTES_IN_DWORD;
}
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OPRTN_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0) + reg_offset, hw_op_val);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0) + reg_offset, data_val);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_DATA_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0) + reg_offset, data_mask);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0) + reg_offset, frame_bit);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_FRAME_MASK_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0) + reg_offset, frame_mask);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_OFFSET_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0) + reg_offset, dword_offset);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_RANGE_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0) + reg_offset, range);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_CYCLIC_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0) + reg_offset, cyclic_bit);
ecore_wr(p_hwfn, p_ptt, (is_filter ? DBG_REG_FILTER_CNSTR_MUST_0 : DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0) + reg_offset, must_bit);
}
/* Reads the specified DBG Bus internal buffer range and copy it to the
* specified buffer. Returns the dumped size in dwords.
*/
static u32 ecore_bus_dump_int_buf_range(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *dump_buf,
bool dump,
u32 start_line,
u32 end_line)
{
u32 line, reg_addr, i, offset = 0;
if (!dump)
return (end_line - start_line + 1) * INT_BUF_LINE_SIZE_IN_DWORDS;
for (line = start_line, reg_addr = DBG_REG_INTR_BUFFER + DWORDS_TO_BYTES(start_line * INT_BUF_LINE_SIZE_IN_DWORDS);
line <= end_line;
line++, offset += INT_BUF_LINE_SIZE_IN_DWORDS)
for (i = 0; i < INT_BUF_LINE_SIZE_IN_DWORDS; i++, reg_addr += BYTES_IN_DWORD)
dump_buf[offset + INT_BUF_LINE_SIZE_IN_DWORDS - 1 - i] = ecore_rd(p_hwfn, p_ptt, reg_addr);
return offset;
}
/* Reads the DBG Bus internal buffer and copy its contents to a buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_bus_dump_int_buf(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *dump_buf,
bool dump)
{
u32 last_written_line, offset = 0;
last_written_line = ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_WR_PTR);
if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_INT_BUFFER)) {
/* Internal buffer was wrapped: first dump from write pointer
* to buffer end, then dump from buffer start to write pointer.
*/
if (last_written_line < INT_BUF_NUM_OF_LINES - 1)
offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, last_written_line + 1, INT_BUF_NUM_OF_LINES - 1);
offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, 0, last_written_line);
}
else if (last_written_line) {
/* Internal buffer wasn't wrapped: dump from buffer start until
* write pointer.
*/
if (!ecore_rd(p_hwfn, p_ptt, DBG_REG_INTR_BUFFER_RD_PTR))
offset += ecore_bus_dump_int_buf_range(p_hwfn, p_ptt, dump_buf + offset, dump, 0, last_written_line);
else
DP_NOTICE(p_hwfn, true, "Unexpected Debug Bus error: internal buffer read pointer is not zero\n");
}
return offset;
}
/* Reads the specified DBG Bus PCI buffer range and copy it to the specified
* buffer. Returns the dumped size in dwords.
*/
static u32 ecore_bus_dump_pci_buf_range(struct ecore_hwfn *p_hwfn,
u32 *dump_buf,
bool dump,
u32 start_line,
u32 end_line)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u32 offset = 0;
/* Extract PCI buffer pointer from virtual address */
void *virt_addr_lo = &dev_data->bus.pci_buf.virt_addr.lo;
u32 *pci_buf_start = (u32*)(osal_uintptr_t)*((u64*)virt_addr_lo);
u32 *pci_buf, line, i;
if (!dump)
return (end_line - start_line + 1) * PCI_BUF_LINE_SIZE_IN_DWORDS;
for (line = start_line, pci_buf = pci_buf_start + start_line * PCI_BUF_LINE_SIZE_IN_DWORDS;
line <= end_line;
line++, offset += PCI_BUF_LINE_SIZE_IN_DWORDS)
for (i = 0; i < PCI_BUF_LINE_SIZE_IN_DWORDS; i++, pci_buf++)
dump_buf[offset + s_pci_buf_line_ind[i]] = *pci_buf;
return offset;
}
/* Copies the DBG Bus PCI buffer to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_bus_dump_pci_buf(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *dump_buf,
bool dump)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u32 next_wr_byte_offset, next_wr_line_offset;
struct dbg_bus_mem_addr next_wr_phys_addr;
u32 pci_buf_size_in_lines, offset = 0;
pci_buf_size_in_lines = dev_data->bus.pci_buf.size / PCI_BUF_LINE_SIZE_IN_BYTES;
/* Extract write pointer (physical address) */
next_wr_phys_addr.lo = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR);
next_wr_phys_addr.hi = ecore_rd(p_hwfn, p_ptt, DBG_REG_EXT_BUFFER_WR_PTR + BYTES_IN_DWORD);
/* Convert write pointer to offset */
next_wr_byte_offset = ecore_phys_addr_diff(&next_wr_phys_addr, &dev_data->bus.pci_buf.phys_addr);
if ((next_wr_byte_offset % PCI_BUF_LINE_SIZE_IN_BYTES) || next_wr_byte_offset > dev_data->bus.pci_buf.size)
return 0;
next_wr_line_offset = next_wr_byte_offset / PCI_BUF_LINE_SIZE_IN_BYTES;
/* PCI buffer wrapped: first dump from write pointer to buffer end. */
if (ecore_rd(p_hwfn, p_ptt, DBG_REG_WRAP_ON_EXT_BUFFER))
offset += ecore_bus_dump_pci_buf_range(p_hwfn, dump_buf + offset, dump, next_wr_line_offset, pci_buf_size_in_lines - 1);
/* Dump from buffer start until write pointer */
if (next_wr_line_offset)
offset += ecore_bus_dump_pci_buf_range(p_hwfn, dump_buf + offset, dump, 0, next_wr_line_offset - 1);
return offset;
}
/* Copies the DBG Bus recorded data to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_bus_dump_data(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *dump_buf,
bool dump)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
switch (dev_data->bus.target) {
case DBG_BUS_TARGET_ID_INT_BUF:
return ecore_bus_dump_int_buf(p_hwfn, p_ptt, dump_buf, dump);
case DBG_BUS_TARGET_ID_PCI:
return ecore_bus_dump_pci_buf(p_hwfn, p_ptt, dump_buf, dump);
default:
break;
}
return 0;
}
/* Frees the Debug Bus PCI buffer */
static void ecore_bus_free_pci_buf(struct ecore_hwfn *p_hwfn)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
dma_addr_t pci_buf_phys_addr;
void *virt_addr_lo;
u32 *pci_buf;
/* Extract PCI buffer pointer from virtual address */
virt_addr_lo = &dev_data->bus.pci_buf.virt_addr.lo;
pci_buf = (u32*)(osal_uintptr_t)*((u64*)virt_addr_lo);
if (!dev_data->bus.pci_buf.size)
return;
OSAL_MEMCPY(&pci_buf_phys_addr, &dev_data->bus.pci_buf.phys_addr, sizeof(pci_buf_phys_addr));
OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, pci_buf, pci_buf_phys_addr, dev_data->bus.pci_buf.size);
dev_data->bus.pci_buf.size = 0;
}
/* Dumps the list of DBG Bus inputs (blocks/Storms) to the specified buffer.
* Returns the dumped size in dwords.
*/
static u32 ecore_bus_dump_inputs(struct ecore_hwfn *p_hwfn,
u32 *dump_buf,
bool dump)