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code.illumos.org / illumos-gate / 3eaaeb3d8421fdd2f5e4d63f0483f6047911215f / . / usr / src / uts / common / io / nvme / nvme.c
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/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
* http://www.illumos.org/license/CDDL.
*/
/*
* Copyright (c) 2016 The MathWorks, Inc. All rights reserved.
* Copyright 2019 Unix Software Ltd.
* Copyright 2020 Joyent, Inc.
* Copyright 2020 Racktop Systems.
* Copyright 2022 Oxide Computer Company.
* Copyright 2022 OmniOS Community Edition (OmniOSce) Association.
* Copyright 2022 Tintri by DDN, Inc. All rights reserved.
*/
/*
* blkdev driver for NVMe compliant storage devices
*
* This driver targets and is designed to support all NVMe 1.x devices.
* Features are added to the driver as we encounter devices that require them
* and our needs, so some commands or log pages may not take advantage of newer
* features that devices support at this time. When you encounter such a case,
* it is generally fine to add that support to the driver as long as you take
* care to ensure that the requisite device version is met before using it.
*
* The driver has only been tested on x86 systems and will not work on big-
* endian systems without changes to the code accessing registers and data
* structures used by the hardware.
*
*
* Interrupt Usage:
*
* The driver will use a single interrupt while configuring the device as the
* specification requires, but contrary to the specification it will try to use
* a single-message MSI(-X) or FIXED interrupt. Later in the attach process it
* will switch to multiple-message MSI(-X) if supported. The driver wants to
* have one interrupt vector per CPU, but it will work correctly if less are
* available. Interrupts can be shared by queues, the interrupt handler will
* iterate through the I/O queue array by steps of n_intr_cnt. Usually only
* the admin queue will share an interrupt with one I/O queue. The interrupt
* handler will retrieve completed commands from all queues sharing an interrupt
* vector and will post them to a taskq for completion processing.
*
*
* Command Processing:
*
* NVMe devices can have up to 65535 I/O queue pairs, with each queue holding up
* to 65536 I/O commands. The driver will configure one I/O queue pair per
* available interrupt vector, with the queue length usually much smaller than
* the maximum of 65536. If the hardware doesn't provide enough queues, fewer
* interrupt vectors will be used.
*
* Additionally the hardware provides a single special admin queue pair that can
* hold up to 4096 admin commands.
*
* From the hardware perspective both queues of a queue pair are independent,
* but they share some driver state: the command array (holding pointers to
* commands currently being processed by the hardware) and the active command
* counter. Access to a submission queue and the shared state is protected by
* nq_mutex; completion queue is protected by ncq_mutex.
*
* When a command is submitted to a queue pair the active command counter is
* incremented and a pointer to the command is stored in the command array. The
* array index is used as command identifier (CID) in the submission queue
* entry. Some commands may take a very long time to complete, and if the queue
* wraps around in that time a submission may find the next array slot to still
* be used by a long-running command. In this case the array is sequentially
* searched for the next free slot. The length of the command array is the same
* as the configured queue length. Queue overrun is prevented by the semaphore,
* so a command submission may block if the queue is full.
*
*
* Polled I/O Support:
*
* For kernel core dump support the driver can do polled I/O. As interrupts are
* turned off while dumping the driver will just submit a command in the regular
* way, and then repeatedly attempt a command retrieval until it gets the
* command back.
*
*
* Namespace Support:
*
* NVMe devices can have multiple namespaces, each being a independent data
* store. The driver supports multiple namespaces and creates a blkdev interface
* for each namespace found. Namespaces can have various attributes to support
* protection information. This driver does not support any of this and ignores
* namespaces that have these attributes.
*
* As of NVMe 1.1 namespaces can have an 64bit Extended Unique Identifier
* (EUI64), and NVMe 1.2 introduced an additional 128bit Namespace Globally
* Unique Identifier (NGUID). This driver uses either the NGUID or the EUI64
* if present to generate the devid, and passes the EUI64 to blkdev to use it
* in the device node names.
*
* We currently support only (2 << NVME_MINOR_INST_SHIFT) - 2 namespaces in a
* single controller. This is an artificial limit imposed by the driver to be
* able to address a reasonable number of controllers and namespaces using a
* 32bit minor node number.
*
*
* Minor nodes:
*
* For each NVMe device the driver exposes one minor node for the controller and
* one minor node for each namespace. The only operations supported by those
* minor nodes are open(9E), close(9E), and ioctl(9E). This serves as the
* interface for the nvmeadm(8) utility.
*
* Exclusive opens are required for certain ioctl(9E) operations that alter
* controller and/or namespace state. While different namespaces may be opened
* exclusively in parallel, an exclusive open of the controller minor node
* requires that no namespaces are currently open (exclusive or otherwise).
* Opening any namespace minor node (exclusive or otherwise) will fail while
* the controller minor node is opened exclusively by any other thread. Thus it
* is possible for one thread at a time to open the controller minor node
* exclusively, and keep it open while opening any namespace minor node of the
* same controller, exclusively or otherwise.
*
*
*
* Blkdev Interface:
*
* This driver uses blkdev to do all the heavy lifting involved with presenting
* a disk device to the system. As a result, the processing of I/O requests is
* relatively simple as blkdev takes care of partitioning, boundary checks, DMA
* setup, and splitting of transfers into manageable chunks.
*
* I/O requests coming in from blkdev are turned into NVM commands and posted to
* an I/O queue. The queue is selected by taking the CPU id modulo the number of
* queues. There is currently no timeout handling of I/O commands.
*
* Blkdev also supports querying device/media information and generating a
* devid. The driver reports the best block size as determined by the namespace
* format back to blkdev as physical block size to support partition and block
* alignment. The devid is either based on the namespace GUID or EUI64, if
* present, or composed using the device vendor ID, model number, serial number,
* and the namespace ID.
*
*
* Error Handling:
*
* Error handling is currently limited to detecting fatal hardware errors,
* either by asynchronous events, or synchronously through command status or
* admin command timeouts. In case of severe errors the device is fenced off,
* all further requests will return EIO. FMA is then called to fault the device.
*
* The hardware has a limit for outstanding asynchronous event requests. Before
* this limit is known the driver assumes it is at least 1 and posts a single
* asynchronous request. Later when the limit is known more asynchronous event
* requests are posted to allow quicker reception of error information. When an
* asynchronous event is posted by the hardware the driver will parse the error
* status fields and log information or fault the device, depending on the
* severity of the asynchronous event. The asynchronous event request is then
* reused and posted to the admin queue again.
*
* On command completion the command status is checked for errors. In case of
* errors indicating a driver bug the driver panics. Almost all other error
* status values just cause EIO to be returned.
*
* Command timeouts are currently detected for all admin commands except
* asynchronous event requests. If a command times out and the hardware appears
* to be healthy the driver attempts to abort the command. The original command
* timeout is also applied to the abort command. If the abort times out too the
* driver assumes the device to be dead, fences it off, and calls FMA to retire
* it. In all other cases the aborted command should return immediately with a
* status indicating it was aborted, and the driver will wait indefinitely for
* that to happen. No timeout handling of normal I/O commands is presently done.
*
* Any command that times out due to the controller dropping dead will be put on
* nvme_lost_cmds list if it references DMA memory. This will prevent the DMA
* memory being reused by the system and later be written to by a "dead" NVMe
* controller.
*
*
* Locking:
*
* Each queue pair has a nq_mutex and ncq_mutex. The nq_mutex must be held
* when accessing shared state and submission queue registers, ncq_mutex
* is held when accessing completion queue state and registers.
* Callers of nvme_unqueue_cmd() must make sure that nq_mutex is held, while
* nvme_submit_{admin,io}_cmd() and nvme_retrieve_cmd() take care of both
* mutexes themselves.
*
* Each command also has its own nc_mutex, which is associated with the
* condition variable nc_cv. It is only used on admin commands which are run
* synchronously. In that case it must be held across calls to
* nvme_submit_{admin,io}_cmd() and nvme_wait_cmd(), which is taken care of by
* nvme_admin_cmd(). It must also be held whenever the completion state of the
* command is changed or while a admin command timeout is handled.
*
* If both nc_mutex and nq_mutex must be held, nc_mutex must be acquired first.
* More than one nc_mutex may only be held when aborting commands. In this case,
* the nc_mutex of the command to be aborted must be held across the call to
* nvme_abort_cmd() to prevent the command from completing while the abort is in
* progress.
*
* If both nq_mutex and ncq_mutex need to be held, ncq_mutex must be
* acquired first. More than one nq_mutex is never held by a single thread.
* The ncq_mutex is only held by nvme_retrieve_cmd() and
* nvme_process_iocq(). nvme_process_iocq() is only called from the
* interrupt thread and nvme_retrieve_cmd() during polled I/O, so the
* mutex is non-contentious but is required for implementation completeness
* and safety.
*
* There is one mutex n_minor_mutex which protects all open flags nm_open and
* exclusive-open thread pointers nm_oexcl of each minor node associated with a
* controller and its namespaces.
*
* In addition, there is one mutex n_mgmt_mutex which must be held whenever the
* driver state for any namespace is changed, especially across calls to
* nvme_init_ns(), nvme_attach_ns() and nvme_detach_ns(). Except when detaching
* nvme, it should also be held across calls that modify the blkdev handle of a
* namespace. Command and queue mutexes may be acquired and released while
* n_mgmt_mutex is held, n_minor_mutex should not.
*
*
* Quiesce / Fast Reboot:
*
* The driver currently does not support fast reboot. A quiesce(9E) entry point
* is still provided which is used to send a shutdown notification to the
* device.
*
*
* NVMe Hotplug:
*
* The driver supports hot removal. The driver uses the NDI event framework
* to register a callback, nvme_remove_callback, to clean up when a disk is
* removed. In particular, the driver will unqueue outstanding I/O commands and
* set n_dead on the softstate to true so that other operations, such as ioctls
* and command submissions, fail as well.
*
* While the callback registration relies on the NDI event framework, the
* removal event itself is kicked off in the PCIe hotplug framework, when the
* PCIe bridge driver ("pcieb") gets a hotplug interrupt indicating that a
* device was removed from the slot.
*
* The NVMe driver instance itself will remain until the final close of the
* device.
*
*
* DDI UFM Support
*
* The driver supports the DDI UFM framework for reporting information about
* the device's firmware image and slot configuration. This data can be
* queried by userland software via ioctls to the ufm driver. For more
* information, see ddi_ufm(9E).
*
*
* Driver Configuration:
*
* The following driver properties can be changed to control some aspects of the
* drivers operation:
* - strict-version: can be set to 0 to allow devices conforming to newer
* major versions to be used
* - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor
* specific command status as a fatal error leading device faulting
* - admin-queue-len: the maximum length of the admin queue (16-4096)
* - io-squeue-len: the maximum length of the I/O submission queues (16-65536)
* - io-cqueue-len: the maximum length of the I/O completion queues (16-65536)
* - async-event-limit: the maximum number of asynchronous event requests to be
* posted by the driver
* - volatile-write-cache-enable: can be set to 0 to disable the volatile write
* cache
* - min-phys-block-size: the minimum physical block size to report to blkdev,
* which is among other things the basis for ZFS vdev ashift
* - max-submission-queues: the maximum number of I/O submission queues.
* - max-completion-queues: the maximum number of I/O completion queues,
* can be less than max-submission-queues, in which case the completion
* queues are shared.
*
* In addition to the above properties, some device-specific tunables can be
* configured using the nvme-config-list global property. The value of this
* property is a list of triplets. The formal syntax is:
*
* nvme-config-list ::= <triplet> [, <triplet>]* ;
* <triplet> ::= "<model>" , "<rev-list>" , "<tuple-list>"
* <rev-list> ::= [ <fwrev> [, <fwrev>]*]
* <tuple-list> ::= <tunable> [, <tunable>]*
* <tunable> ::= <name> : <value>
*
* The <model> and <fwrev> are the strings in nvme_identify_ctrl_t`id_model and
* nvme_identify_ctrl_t`id_fwrev, respectively. The remainder of <tuple-list>
* contains one or more tunables to apply to all controllers that match the
* specified model number and optionally firmware revision. Each <tunable> is a
* <name> : <value> pair. Supported tunables are:
*
* - ignore-unknown-vendor-status: can be set to "on" to not handle any vendor
* specific command status as a fatal error leading device faulting
*
* - min-phys-block-size: the minimum physical block size to report to blkdev,
* which is among other things the basis for ZFS vdev ashift
*
* - volatile-write-cache: can be set to "on" or "off" to enable or disable the
* volatile write cache, if present
*
*
* TODO:
* - figure out sane default for I/O queue depth reported to blkdev
* - FMA handling of media errors
* - support for devices supporting very large I/O requests using chained PRPs
* - support for configuring hardware parameters like interrupt coalescing
* - support for media formatting and hard partitioning into namespaces
* - support for big-endian systems
* - support for fast reboot
* - support for NVMe Subsystem Reset (1.1)
* - support for Scatter/Gather lists (1.1)
* - support for Reservations (1.1)
* - support for power management
*/
#include <sys/byteorder.h>
#ifdef _BIG_ENDIAN
#error nvme driver needs porting for big-endian platforms
#endif
#include <sys/modctl.h>
#include <sys/conf.h>
#include <sys/devops.h>
#include <sys/ddi.h>
#include <sys/ddi_ufm.h>
#include <sys/sunddi.h>
#include <sys/sunndi.h>
#include <sys/bitmap.h>
#include <sys/sysmacros.h>
#include <sys/param.h>
#include <sys/varargs.h>
#include <sys/cpuvar.h>
#include <sys/disp.h>
#include <sys/blkdev.h>
#include <sys/atomic.h>
#include <sys/archsystm.h>
#include <sys/sata/sata_hba.h>
#include <sys/stat.h>
#include <sys/policy.h>
#include <sys/list.h>
#include <sys/dkio.h>
#include <sys/nvme.h>
#ifdef __x86
#include <sys/x86_archext.h>
#endif
#include "nvme_reg.h"
#include "nvme_var.h"
/*
* Assertions to make sure that we've properly captured various aspects of the
* packed structures and haven't broken them during updates.
*/
CTASSERT(sizeof (nvme_identify_ctrl_t) == NVME_IDENTIFY_BUFSIZE);
CTASSERT(offsetof(nvme_identify_ctrl_t, id_oacs) == 256);
CTASSERT(offsetof(nvme_identify_ctrl_t, id_sqes) == 512);
CTASSERT(offsetof(nvme_identify_ctrl_t, id_oncs) == 520);
CTASSERT(offsetof(nvme_identify_ctrl_t, id_subnqn) == 768);
CTASSERT(offsetof(nvme_identify_ctrl_t, id_nvmof) == 1792);
CTASSERT(offsetof(nvme_identify_ctrl_t, id_psd) == 2048);
CTASSERT(offsetof(nvme_identify_ctrl_t, id_vs) == 3072);
CTASSERT(sizeof (nvme_identify_nsid_t) == NVME_IDENTIFY_BUFSIZE);
CTASSERT(offsetof(nvme_identify_nsid_t, id_fpi) == 32);
CTASSERT(offsetof(nvme_identify_nsid_t, id_anagrpid) == 92);
CTASSERT(offsetof(nvme_identify_nsid_t, id_nguid) == 104);
CTASSERT(offsetof(nvme_identify_nsid_t, id_lbaf) == 128);
CTASSERT(offsetof(nvme_identify_nsid_t, id_vs) == 384);
CTASSERT(sizeof (nvme_identify_nsid_list_t) == NVME_IDENTIFY_BUFSIZE);
CTASSERT(sizeof (nvme_identify_ctrl_list_t) == NVME_IDENTIFY_BUFSIZE);
CTASSERT(sizeof (nvme_identify_primary_caps_t) == NVME_IDENTIFY_BUFSIZE);
CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vqfrt) == 32);
CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vifrt) == 64);
CTASSERT(sizeof (nvme_nschange_list_t) == 4096);
/* NVMe spec version supported */
static const int nvme_version_major = 1;
/* tunable for admin command timeout in seconds, default is 1s */
int nvme_admin_cmd_timeout = 1;
/* tunable for FORMAT NVM command timeout in seconds, default is 600s */
int nvme_format_cmd_timeout = 600;
/* tunable for firmware commit with NVME_FWC_SAVE, default is 15s */
int nvme_commit_save_cmd_timeout = 15;
/*
* tunable for the size of arbitrary vendor specific admin commands,
* default is 16MiB.
*/
uint32_t nvme_vendor_specific_admin_cmd_size = 1 << 24;
/*
* tunable for the max timeout of arbitary vendor specific admin commands,
* default is 60s.
*/
uint_t nvme_vendor_specific_admin_cmd_max_timeout = 60;
static int nvme_attach(dev_info_t *, ddi_attach_cmd_t);
static int nvme_detach(dev_info_t *, ddi_detach_cmd_t);
static int nvme_quiesce(dev_info_t *);
static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *);
static int nvme_setup_interrupts(nvme_t *, int, int);
static void nvme_release_interrupts(nvme_t *);
static uint_t nvme_intr(caddr_t, caddr_t);
static void nvme_shutdown(nvme_t *, int, boolean_t);
static boolean_t nvme_reset(nvme_t *, boolean_t);
static int nvme_init(nvme_t *);
static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int);
static void nvme_free_cmd(nvme_cmd_t *);
static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t,
bd_xfer_t *);
static void nvme_admin_cmd(nvme_cmd_t *, int);
static void nvme_submit_admin_cmd(nvme_qpair_t *, nvme_cmd_t *);
static int nvme_submit_io_cmd(nvme_qpair_t *, nvme_cmd_t *);
static void nvme_submit_cmd_common(nvme_qpair_t *, nvme_cmd_t *);
static nvme_cmd_t *nvme_unqueue_cmd(nvme_t *, nvme_qpair_t *, int);
static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *);
static void nvme_wait_cmd(nvme_cmd_t *, uint_t);
static void nvme_wakeup_cmd(void *);
static void nvme_async_event_task(void *);
static int nvme_check_unknown_cmd_status(nvme_cmd_t *);
static int nvme_check_vendor_cmd_status(nvme_cmd_t *);
static int nvme_check_integrity_cmd_status(nvme_cmd_t *);
static int nvme_check_specific_cmd_status(nvme_cmd_t *);
static int nvme_check_generic_cmd_status(nvme_cmd_t *);
static inline int nvme_check_cmd_status(nvme_cmd_t *);
static int nvme_abort_cmd(nvme_cmd_t *, uint_t);
static void nvme_async_event(nvme_t *);
static int nvme_format_nvm(nvme_t *, boolean_t, uint32_t, uint8_t, boolean_t,
uint8_t, boolean_t, uint8_t);
static int nvme_get_logpage(nvme_t *, boolean_t, void **, size_t *, uint8_t,
...);
static int nvme_identify(nvme_t *, boolean_t, uint32_t, uint8_t, void **);
static int nvme_set_features(nvme_t *, boolean_t, uint32_t, uint8_t, uint32_t,
uint32_t *);
static int nvme_get_features(nvme_t *, boolean_t, uint32_t, uint8_t, uint32_t *,
void **, size_t *);
static int nvme_write_cache_set(nvme_t *, boolean_t);
static int nvme_set_nqueues(nvme_t *);
static void nvme_free_dma(nvme_dma_t *);
static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *,
nvme_dma_t **);
static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t,
nvme_dma_t **);
static void nvme_free_qpair(nvme_qpair_t *);
static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, uint_t);
static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t);
static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t);
static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t);
static inline uint64_t nvme_get64(nvme_t *, uintptr_t);
static inline uint32_t nvme_get32(nvme_t *, uintptr_t);
static boolean_t nvme_check_regs_hdl(nvme_t *);
static boolean_t nvme_check_dma_hdl(nvme_dma_t *);
static int nvme_fill_prp(nvme_cmd_t *, ddi_dma_handle_t);
static void nvme_bd_xfer_done(void *);
static void nvme_bd_driveinfo(void *, bd_drive_t *);
static int nvme_bd_mediainfo(void *, bd_media_t *);
static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t);
static int nvme_bd_read(void *, bd_xfer_t *);
static int nvme_bd_write(void *, bd_xfer_t *);
static int nvme_bd_sync(void *, bd_xfer_t *);
static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *);
static int nvme_bd_free_space(void *, bd_xfer_t *);
static int nvme_prp_dma_constructor(void *, void *, int);
static void nvme_prp_dma_destructor(void *, void *);
static void nvme_prepare_devid(nvme_t *, uint32_t);
/* DDI UFM callbacks */
static int nvme_ufm_fill_image(ddi_ufm_handle_t *, void *, uint_t,
ddi_ufm_image_t *);
static int nvme_ufm_fill_slot(ddi_ufm_handle_t *, void *, uint_t, uint_t,
ddi_ufm_slot_t *);
static int nvme_ufm_getcaps(ddi_ufm_handle_t *, void *, ddi_ufm_cap_t *);
static int nvme_open(dev_t *, int, int, cred_t *);
static int nvme_close(dev_t, int, int, cred_t *);
static int nvme_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
static int nvme_init_ns(nvme_t *, int);
static int nvme_attach_ns(nvme_t *, int);
static int nvme_detach_ns(nvme_t *, int);
#define NVME_NSID2NS(nvme, nsid) (&((nvme)->n_ns[(nsid) - 1]))
static ddi_ufm_ops_t nvme_ufm_ops = {
NULL,
nvme_ufm_fill_image,
nvme_ufm_fill_slot,
nvme_ufm_getcaps
};
#define NVME_MINOR_INST_SHIFT 9
#define NVME_MINOR(inst, nsid) (((inst) << NVME_MINOR_INST_SHIFT) | (nsid))
#define NVME_MINOR_INST(minor) ((minor) >> NVME_MINOR_INST_SHIFT)
#define NVME_MINOR_NSID(minor) ((minor) & ((1 << NVME_MINOR_INST_SHIFT) - 1))
#define NVME_MINOR_MAX (NVME_MINOR(1, 0) - 2)
#define NVME_IS_VENDOR_SPECIFIC_CMD(x) (((x) >= 0xC0) && ((x) <= 0xFF))
#define NVME_VENDOR_SPECIFIC_LOGPAGE_MIN 0xC0
#define NVME_VENDOR_SPECIFIC_LOGPAGE_MAX 0xFF
#define NVME_IS_VENDOR_SPECIFIC_LOGPAGE(x) \
(((x) >= NVME_VENDOR_SPECIFIC_LOGPAGE_MIN) && \
((x) <= NVME_VENDOR_SPECIFIC_LOGPAGE_MAX))
/*
* NVMe versions 1.3 and later actually support log pages up to UINT32_MAX
* DWords in size. However, revision 1.3 also modified the layout of the Get Log
* Page command significantly relative to version 1.2, including changing
* reserved bits, adding new bitfields, and requiring the use of command DWord
* 11 to fully specify the size of the log page (the lower and upper 16 bits of
* the number of DWords in the page are split between DWord 10 and DWord 11,
* respectively).
*
* All of these impose significantly different layout requirements on the
* `nvme_getlogpage_t` type. This could be solved with two different types, or a
* complicated/nested union with the two versions as the overlying members. Both
* of these are reasonable, if a bit convoluted. However, these is no current
* need for such large pages, or a way to test them, as most log pages actually
* fit within the current size limit. So for simplicity, we retain the size cap
* from version 1.2.
*
* Note that the number of DWords is zero-based, so we add 1. It is subtracted
* to form a zero-based value in `nvme_get_logpage`.
*/
#define NVME_VENDOR_SPECIFIC_LOGPAGE_MAX_SIZE \
(((1 << 12) + 1) * sizeof (uint32_t))
static void *nvme_state;
static kmem_cache_t *nvme_cmd_cache;
/*
* DMA attributes for queue DMA memory
*
* Queue DMA memory must be page aligned. The maximum length of a queue is
* 65536 entries, and an entry can be 64 bytes long.
*/
static ddi_dma_attr_t nvme_queue_dma_attr = {
.dma_attr_version = DMA_ATTR_V0,
.dma_attr_addr_lo = 0,
.dma_attr_addr_hi = 0xffffffffffffffffULL,
.dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1,
.dma_attr_align = 0x1000,
.dma_attr_burstsizes = 0x7ff,
.dma_attr_minxfer = 0x1000,
.dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t),
.dma_attr_seg = 0xffffffffffffffffULL,
.dma_attr_sgllen = 1,
.dma_attr_granular = 1,
.dma_attr_flags = 0,
};
/*
* DMA attributes for transfers using Physical Region Page (PRP) entries
*
* A PRP entry describes one page of DMA memory using the page size specified
* in the controller configuration's memory page size register (CC.MPS). It uses
* a 64bit base address aligned to this page size. There is no limitation on
* chaining PRPs together for arbitrarily large DMA transfers.
*/
static ddi_dma_attr_t nvme_prp_dma_attr = {
.dma_attr_version = DMA_ATTR_V0,
.dma_attr_addr_lo = 0,
.dma_attr_addr_hi = 0xffffffffffffffffULL,
.dma_attr_count_max = 0xfff,
.dma_attr_align = 0x1000,
.dma_attr_burstsizes = 0x7ff,
.dma_attr_minxfer = 0x1000,
.dma_attr_maxxfer = 0x1000,
.dma_attr_seg = 0xfff,
.dma_attr_sgllen = -1,
.dma_attr_granular = 1,
.dma_attr_flags = 0,
};
/*
* DMA attributes for transfers using scatter/gather lists
*
* A SGL entry describes a chunk of DMA memory using a 64bit base address and a
* 32bit length field. SGL Segment and SGL Last Segment entries require the
* length to be a multiple of 16 bytes.
*/
static ddi_dma_attr_t nvme_sgl_dma_attr = {
.dma_attr_version = DMA_ATTR_V0,
.dma_attr_addr_lo = 0,
.dma_attr_addr_hi = 0xffffffffffffffffULL,
.dma_attr_count_max = 0xffffffffUL,
.dma_attr_align = 1,
.dma_attr_burstsizes = 0x7ff,
.dma_attr_minxfer = 0x10,
.dma_attr_maxxfer = 0xfffffffffULL,
.dma_attr_seg = 0xffffffffffffffffULL,
.dma_attr_sgllen = -1,
.dma_attr_granular = 0x10,
.dma_attr_flags = 0
};
static ddi_device_acc_attr_t nvme_reg_acc_attr = {
.devacc_attr_version = DDI_DEVICE_ATTR_V0,
.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC,
.devacc_attr_dataorder = DDI_STRICTORDER_ACC
};
static struct cb_ops nvme_cb_ops = {
.cb_open = nvme_open,
.cb_close = nvme_close,
.cb_strategy = nodev,
.cb_print = nodev,
.cb_dump = nodev,
.cb_read = nodev,
.cb_write = nodev,
.cb_ioctl = nvme_ioctl,
.cb_devmap = nodev,
.cb_mmap = nodev,
.cb_segmap = nodev,
.cb_chpoll = nochpoll,
.cb_prop_op = ddi_prop_op,
.cb_str = 0,
.cb_flag = D_NEW | D_MP,
.cb_rev = CB_REV,
.cb_aread = nodev,
.cb_awrite = nodev
};
static struct dev_ops nvme_dev_ops = {
.devo_rev = DEVO_REV,
.devo_refcnt = 0,
.devo_getinfo = ddi_no_info,
.devo_identify = nulldev,
.devo_probe = nulldev,
.devo_attach = nvme_attach,
.devo_detach = nvme_detach,
.devo_reset = nodev,
.devo_cb_ops = &nvme_cb_ops,
.devo_bus_ops = NULL,
.devo_power = NULL,
.devo_quiesce = nvme_quiesce,
};
static struct modldrv nvme_modldrv = {
.drv_modops = &mod_driverops,
.drv_linkinfo = "NVMe v1.1b",
.drv_dev_ops = &nvme_dev_ops
};
static struct modlinkage nvme_modlinkage = {
.ml_rev = MODREV_1,
.ml_linkage = { &nvme_modldrv, NULL }
};
static bd_ops_t nvme_bd_ops = {
.o_version = BD_OPS_CURRENT_VERSION,
.o_drive_info = nvme_bd_driveinfo,
.o_media_info = nvme_bd_mediainfo,
.o_devid_init = nvme_bd_devid,
.o_sync_cache = nvme_bd_sync,
.o_read = nvme_bd_read,
.o_write = nvme_bd_write,
.o_free_space = nvme_bd_free_space,
};
/*
* This list will hold commands that have timed out and couldn't be aborted.
* As we don't know what the hardware may still do with the DMA memory we can't
* free them, so we'll keep them forever on this list where we can easily look
* at them with mdb.
*/
static struct list nvme_lost_cmds;
static kmutex_t nvme_lc_mutex;
int
_init(void)
{
int error;
error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1);
if (error != DDI_SUCCESS)
return (error);
nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache",
sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0);
mutex_init(&nvme_lc_mutex, NULL, MUTEX_DRIVER, NULL);
list_create(&nvme_lost_cmds, sizeof (nvme_cmd_t),
offsetof(nvme_cmd_t, nc_list));
bd_mod_init(&nvme_dev_ops);
error = mod_install(&nvme_modlinkage);
if (error != DDI_SUCCESS) {
ddi_soft_state_fini(&nvme_state);
mutex_destroy(&nvme_lc_mutex);
list_destroy(&nvme_lost_cmds);
bd_mod_fini(&nvme_dev_ops);
}
return (error);
}
int
_fini(void)
{
int error;
if (!list_is_empty(&nvme_lost_cmds))
return (DDI_FAILURE);
error = mod_remove(&nvme_modlinkage);
if (error == DDI_SUCCESS) {
ddi_soft_state_fini(&nvme_state);
kmem_cache_destroy(nvme_cmd_cache);
mutex_destroy(&nvme_lc_mutex);
list_destroy(&nvme_lost_cmds);
bd_mod_fini(&nvme_dev_ops);
}
return (error);
}
int
_info(struct modinfo *modinfop)
{
return (mod_info(&nvme_modlinkage, modinfop));
}
static inline void
nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
{
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
/*LINTED: E_BAD_PTR_CAST_ALIGN*/
ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
}
static inline void
nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
{
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
/*LINTED: E_BAD_PTR_CAST_ALIGN*/
ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
}
static inline uint64_t
nvme_get64(nvme_t *nvme, uintptr_t reg)
{
uint64_t val;
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
/*LINTED: E_BAD_PTR_CAST_ALIGN*/
val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
return (val);
}
static inline uint32_t
nvme_get32(nvme_t *nvme, uintptr_t reg)
{
uint32_t val;
ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
/*LINTED: E_BAD_PTR_CAST_ALIGN*/
val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
return (val);
}
static boolean_t
nvme_check_regs_hdl(nvme_t *nvme)
{
ddi_fm_error_t error;
ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION);
if (error.fme_status != DDI_FM_OK)
return (B_TRUE);
return (B_FALSE);
}
static boolean_t
nvme_check_dma_hdl(nvme_dma_t *dma)
{
ddi_fm_error_t error;
if (dma == NULL)
return (B_FALSE);
ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION);
if (error.fme_status != DDI_FM_OK)
return (B_TRUE);
return (B_FALSE);
}
static void
nvme_free_dma_common(nvme_dma_t *dma)
{
if (dma->nd_dmah != NULL)
(void) ddi_dma_unbind_handle(dma->nd_dmah);
if (dma->nd_acch != NULL)
ddi_dma_mem_free(&dma->nd_acch);
if (dma->nd_dmah != NULL)
ddi_dma_free_handle(&dma->nd_dmah);
}
static void
nvme_free_dma(nvme_dma_t *dma)
{
nvme_free_dma_common(dma);
kmem_free(dma, sizeof (*dma));
}
/* ARGSUSED */
static void
nvme_prp_dma_destructor(void *buf, void *private)
{
nvme_dma_t *dma = (nvme_dma_t *)buf;
nvme_free_dma_common(dma);
}
static int
nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma,
size_t len, uint_t flags, ddi_dma_attr_t *dma_attr)
{
if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL,
&dma->nd_dmah) != DDI_SUCCESS) {
/*
* Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and
* the only other possible error is DDI_DMA_BADATTR which
* indicates a driver bug which should cause a panic.
*/
dev_err(nvme->n_dip, CE_PANIC,
"!failed to get DMA handle, check DMA attributes");
return (DDI_FAILURE);
}
/*
* ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified
* or the flags are conflicting, which isn't the case here.
*/
(void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr,
DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp,
&dma->nd_len, &dma->nd_acch);
if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp,
dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
&dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) {
dev_err(nvme->n_dip, CE_WARN,
"!failed to bind DMA memory");
atomic_inc_32(&nvme->n_dma_bind_err);
nvme_free_dma_common(dma);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
static int
nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
{
nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) !=
DDI_SUCCESS) {
*ret = NULL;
kmem_free(dma, sizeof (nvme_dma_t));
return (DDI_FAILURE);
}
bzero(dma->nd_memp, dma->nd_len);
*ret = dma;
return (DDI_SUCCESS);
}
/* ARGSUSED */
static int
nvme_prp_dma_constructor(void *buf, void *private, int flags)
{
nvme_dma_t *dma = (nvme_dma_t *)buf;
nvme_t *nvme = (nvme_t *)private;
dma->nd_dmah = NULL;
dma->nd_acch = NULL;
if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize,
DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) {
return (-1);
}
ASSERT(dma->nd_ncookie == 1);
dma->nd_cached = B_TRUE;
return (0);
}
static int
nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len,
uint_t flags, nvme_dma_t **dma)
{
uint32_t len = nentry * qe_len;
ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr;
len = roundup(len, nvme->n_pagesize);
if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma)
!= DDI_SUCCESS) {
dev_err(nvme->n_dip, CE_WARN,
"!failed to get DMA memory for queue");
goto fail;
}
if ((*dma)->nd_ncookie != 1) {
dev_err(nvme->n_dip, CE_WARN,
"!got too many cookies for queue DMA");
goto fail;
}
return (DDI_SUCCESS);
fail:
if (*dma) {
nvme_free_dma(*dma);
*dma = NULL;
}
return (DDI_FAILURE);
}
static void
nvme_free_cq(nvme_cq_t *cq)
{
mutex_destroy(&cq->ncq_mutex);
if (cq->ncq_cmd_taskq != NULL)
taskq_destroy(cq->ncq_cmd_taskq);
if (cq->ncq_dma != NULL)
nvme_free_dma(cq->ncq_dma);
kmem_free(cq, sizeof (*cq));
}
static void
nvme_free_qpair(nvme_qpair_t *qp)
{
int i;
mutex_destroy(&qp->nq_mutex);
sema_destroy(&qp->nq_sema);
if (qp->nq_sqdma != NULL)
nvme_free_dma(qp->nq_sqdma);
if (qp->nq_active_cmds > 0)
for (i = 0; i != qp->nq_nentry; i++)
if (qp->nq_cmd[i] != NULL)
nvme_free_cmd(qp->nq_cmd[i]);
if (qp->nq_cmd != NULL)
kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry);
kmem_free(qp, sizeof (nvme_qpair_t));
}
/*
* Destroy the pre-allocated cq array, but only free individual completion
* queues from the given starting index.
*/
static void
nvme_destroy_cq_array(nvme_t *nvme, uint_t start)
{
uint_t i;
for (i = start; i < nvme->n_cq_count; i++)
if (nvme->n_cq[i] != NULL)
nvme_free_cq(nvme->n_cq[i]);
kmem_free(nvme->n_cq, sizeof (*nvme->n_cq) * nvme->n_cq_count);
}
static int
nvme_alloc_cq(nvme_t *nvme, uint32_t nentry, nvme_cq_t **cqp, uint16_t idx,
uint_t nthr)
{
nvme_cq_t *cq = kmem_zalloc(sizeof (*cq), KM_SLEEP);
char name[64]; /* large enough for the taskq name */
mutex_init(&cq->ncq_mutex, NULL, MUTEX_DRIVER,
DDI_INTR_PRI(nvme->n_intr_pri));
if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t),
DDI_DMA_READ, &cq->ncq_dma) != DDI_SUCCESS)
goto fail;
cq->ncq_cq = (nvme_cqe_t *)cq->ncq_dma->nd_memp;
cq->ncq_nentry = nentry;
cq->ncq_id = idx;
cq->ncq_hdbl = NVME_REG_CQHDBL(nvme, idx);
/*
* Each completion queue has its own command taskq.
*/
(void) snprintf(name, sizeof (name), "%s%d_cmd_taskq%u",
ddi_driver_name(nvme->n_dip), ddi_get_instance(nvme->n_dip), idx);
cq->ncq_cmd_taskq = taskq_create(name, nthr, minclsyspri, 64, INT_MAX,
TASKQ_PREPOPULATE);
if (cq->ncq_cmd_taskq == NULL) {
dev_err(nvme->n_dip, CE_WARN, "!failed to create cmd "
"taskq for cq %u", idx);
goto fail;
}
*cqp = cq;
return (DDI_SUCCESS);
fail:
nvme_free_cq(cq);
*cqp = NULL;
return (DDI_FAILURE);
}
/*
* Create the n_cq array big enough to hold "ncq" completion queues.
* If the array already exists it will be re-sized (but only larger).
* The admin queue is included in this array, which boosts the
* max number of entries to UINT16_MAX + 1.
*/
static int
nvme_create_cq_array(nvme_t *nvme, uint_t ncq, uint32_t nentry, uint_t nthr)
{
nvme_cq_t **cq;
uint_t i, cq_count;
ASSERT3U(ncq, >, nvme->n_cq_count);
cq = nvme->n_cq;
cq_count = nvme->n_cq_count;
nvme->n_cq = kmem_zalloc(sizeof (*nvme->n_cq) * ncq, KM_SLEEP);
nvme->n_cq_count = ncq;
for (i = 0; i < cq_count; i++)
nvme->n_cq[i] = cq[i];
for (; i < nvme->n_cq_count; i++)
if (nvme_alloc_cq(nvme, nentry, &nvme->n_cq[i], i, nthr) !=
DDI_SUCCESS)
goto fail;
if (cq != NULL)
kmem_free(cq, sizeof (*cq) * cq_count);
return (DDI_SUCCESS);
fail:
nvme_destroy_cq_array(nvme, cq_count);
/*
* Restore the original array
*/
nvme->n_cq_count = cq_count;
nvme->n_cq = cq;
return (DDI_FAILURE);
}
static int
nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp,
uint_t idx)
{
nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP);
uint_t cq_idx;
mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER,
DDI_INTR_PRI(nvme->n_intr_pri));
/*
* The NVMe spec defines that a full queue has one empty (unused) slot;
* initialize the semaphore accordingly.
*/
sema_init(&qp->nq_sema, nentry - 1, NULL, SEMA_DRIVER, NULL);
if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t),
DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS)
goto fail;
/*
* idx == 0 is adminq, those above 0 are shared io completion queues.
*/
cq_idx = idx == 0 ? 0 : 1 + (idx - 1) % (nvme->n_cq_count - 1);
qp->nq_cq = nvme->n_cq[cq_idx];
qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp;
qp->nq_nentry = nentry;
qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx);
qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP);
qp->nq_next_cmd = 0;
*nqp = qp;
return (DDI_SUCCESS);
fail:
nvme_free_qpair(qp);
*nqp = NULL;
return (DDI_FAILURE);
}
static nvme_cmd_t *
nvme_alloc_cmd(nvme_t *nvme, int kmflag)
{
nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag);
if (cmd == NULL)
return (cmd);
bzero(cmd, sizeof (nvme_cmd_t));
cmd->nc_nvme = nvme;
mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER,
DDI_INTR_PRI(nvme->n_intr_pri));
cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL);
return (cmd);
}
static void
nvme_free_cmd(nvme_cmd_t *cmd)
{
/* Don't free commands on the lost commands list. */
if (list_link_active(&cmd->nc_list))
return;
if (cmd->nc_dma) {
nvme_free_dma(cmd->nc_dma);
cmd->nc_dma = NULL;
}
if (cmd->nc_prp) {
kmem_cache_free(cmd->nc_nvme->n_prp_cache, cmd->nc_prp);
cmd->nc_prp = NULL;
}
cv_destroy(&cmd->nc_cv);
mutex_destroy(&cmd->nc_mutex);
kmem_cache_free(nvme_cmd_cache, cmd);
}
static void
nvme_submit_admin_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
{
sema_p(&qp->nq_sema);
nvme_submit_cmd_common(qp, cmd);
}
static int
nvme_submit_io_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
{
if (cmd->nc_nvme->n_dead) {
return (EIO);
}
if (sema_tryp(&qp->nq_sema) == 0)
return (EAGAIN);
nvme_submit_cmd_common(qp, cmd);
return (0);
}
static void
nvme_submit_cmd_common(nvme_qpair_t *qp, nvme_cmd_t *cmd)
{
nvme_reg_sqtdbl_t tail = { 0 };
mutex_enter(&qp->nq_mutex);
cmd->nc_completed = B_FALSE;
/*
* Now that we hold the queue pair lock, we must check whether or not
* the controller has been listed as dead (e.g. was removed due to
* hotplug). This is necessary as otherwise we could race with
* nvme_remove_callback(). Because this has not been enqueued, we don't
* call nvme_unqueue_cmd(), which is why we must manually decrement the
* semaphore.
*/
if (cmd->nc_nvme->n_dead) {
taskq_dispatch_ent(qp->nq_cq->ncq_cmd_taskq, cmd->nc_callback,
cmd, TQ_NOSLEEP, &cmd->nc_tqent);
sema_v(&qp->nq_sema);
mutex_exit(&qp->nq_mutex);
return;
}
/*
* Try to insert the cmd into the active cmd array at the nq_next_cmd
* slot. If the slot is already occupied advance to the next slot and
* try again. This can happen for long running commands like async event
* requests.
*/
while (qp->nq_cmd[qp->nq_next_cmd] != NULL)
qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
qp->nq_cmd[qp->nq_next_cmd] = cmd;
qp->nq_active_cmds++;
cmd->nc_sqe.sqe_cid = qp->nq_next_cmd;
bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t));
(void) ddi_dma_sync(qp->nq_sqdma->nd_dmah,
sizeof (nvme_sqe_t) * qp->nq_sqtail,
sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV);
qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry;
nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r);
mutex_exit(&qp->nq_mutex);
}
static nvme_cmd_t *
nvme_unqueue_cmd(nvme_t *nvme, nvme_qpair_t *qp, int cid)
{
nvme_cmd_t *cmd;
ASSERT(mutex_owned(&qp->nq_mutex));
ASSERT3S(cid, <, qp->nq_nentry);
cmd = qp->nq_cmd[cid];
qp->nq_cmd[cid] = NULL;
ASSERT3U(qp->nq_active_cmds, >, 0);
qp->nq_active_cmds--;
sema_v(&qp->nq_sema);
ASSERT3P(cmd, !=, NULL);
ASSERT3P(cmd->nc_nvme, ==, nvme);
ASSERT3S(cmd->nc_sqe.sqe_cid, ==, cid);
return (cmd);
}
/*
* Get the command tied to the next completed cqe and bump along completion
* queue head counter.
*/
static nvme_cmd_t *
nvme_get_completed(nvme_t *nvme, nvme_cq_t *cq)
{
nvme_qpair_t *qp;
nvme_cqe_t *cqe;
nvme_cmd_t *cmd;
ASSERT(mutex_owned(&cq->ncq_mutex));
cqe = &cq->ncq_cq[cq->ncq_head];
/* Check phase tag of CQE. Hardware inverts it for new entries. */
if (cqe->cqe_sf.sf_p == cq->ncq_phase)
return (NULL);
qp = nvme->n_ioq[cqe->cqe_sqid];
mutex_enter(&qp->nq_mutex);
cmd = nvme_unqueue_cmd(nvme, qp, cqe->cqe_cid);
mutex_exit(&qp->nq_mutex);
ASSERT(cmd->nc_sqid == cqe->cqe_sqid);
bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t));
qp->nq_sqhead = cqe->cqe_sqhd;
cq->ncq_head = (cq->ncq_head + 1) % cq->ncq_nentry;
/* Toggle phase on wrap-around. */
if (cq->ncq_head == 0)
cq->ncq_phase = cq->ncq_phase ? 0 : 1;
return (cmd);
}
/*
* Process all completed commands on the io completion queue.
*/
static uint_t
nvme_process_iocq(nvme_t *nvme, nvme_cq_t *cq)
{
nvme_reg_cqhdbl_t head = { 0 };
nvme_cmd_t *cmd;
uint_t completed = 0;
if (ddi_dma_sync(cq->ncq_dma->nd_dmah, 0, 0, DDI_DMA_SYNC_FORKERNEL) !=
DDI_SUCCESS)
dev_err(nvme->n_dip, CE_WARN, "!ddi_dma_sync() failed in %s",
__func__);
mutex_enter(&cq->ncq_mutex);
while ((cmd = nvme_get_completed(nvme, cq)) != NULL) {
taskq_dispatch_ent(cq->ncq_cmd_taskq, cmd->nc_callback, cmd,
TQ_NOSLEEP, &cmd->nc_tqent);
completed++;
}
if (completed > 0) {
/*
* Update the completion queue head doorbell.
*/
head.b.cqhdbl_cqh = cq->ncq_head;
nvme_put32(nvme, cq->ncq_hdbl, head.r);
}
mutex_exit(&cq->ncq_mutex);
return (completed);
}
static nvme_cmd_t *
nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp)
{
nvme_cq_t *cq = qp->nq_cq;
nvme_reg_cqhdbl_t head = { 0 };
nvme_cmd_t *cmd;
if (ddi_dma_sync(cq->ncq_dma->nd_dmah, 0, 0, DDI_DMA_SYNC_FORKERNEL) !=
DDI_SUCCESS)
dev_err(nvme->n_dip, CE_WARN, "!ddi_dma_sync() failed in %s",
__func__);
mutex_enter(&cq->ncq_mutex);
if ((cmd = nvme_get_completed(nvme, cq)) != NULL) {
head.b.cqhdbl_cqh = cq->ncq_head;
nvme_put32(nvme, cq->ncq_hdbl, head.r);
}
mutex_exit(&cq->ncq_mutex);
return (cmd);
}
static int
nvme_check_unknown_cmd_status(nvme_cmd_t *cmd)
{
nvme_cqe_t *cqe = &cmd->nc_cqe;
dev_err(cmd->nc_nvme->n_dip, CE_WARN,
"!unknown command status received: opc = %x, sqid = %d, cid = %d, "
"sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
if (cmd->nc_nvme->n_strict_version) {
cmd->nc_nvme->n_dead = B_TRUE;
ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
}
return (EIO);
}
static int
nvme_check_vendor_cmd_status(nvme_cmd_t *cmd)
{
nvme_cqe_t *cqe = &cmd->nc_cqe;
dev_err(cmd->nc_nvme->n_dip, CE_WARN,
"!unknown command status received: opc = %x, sqid = %d, cid = %d, "
"sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) {
cmd->nc_nvme->n_dead = B_TRUE;
ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
}
return (EIO);
}
static int
nvme_check_integrity_cmd_status(nvme_cmd_t *cmd)
{
nvme_cqe_t *cqe = &cmd->nc_cqe;
switch (cqe->cqe_sf.sf_sc) {
case NVME_CQE_SC_INT_NVM_WRITE:
/* write fail */
/* TODO: post ereport */
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
return (EIO);
case NVME_CQE_SC_INT_NVM_READ:
/* read fail */
/* TODO: post ereport */
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
return (EIO);
default:
return (nvme_check_unknown_cmd_status(cmd));
}
}
static int
nvme_check_generic_cmd_status(nvme_cmd_t *cmd)
{
nvme_cqe_t *cqe = &cmd->nc_cqe;
switch (cqe->cqe_sf.sf_sc) {
case NVME_CQE_SC_GEN_SUCCESS:
return (0);
/*
* Errors indicating a bug in the driver should cause a panic.
*/
case NVME_CQE_SC_GEN_INV_OPC:
/* Invalid Command Opcode */
if (!cmd->nc_dontpanic)
dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
"programming error: invalid opcode in cmd %p",
(void *)cmd);
return (EINVAL);
case NVME_CQE_SC_GEN_INV_FLD:
/* Invalid Field in Command */
if (!cmd->nc_dontpanic)
dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
"programming error: invalid field in cmd %p",
(void *)cmd);
return (EIO);
case NVME_CQE_SC_GEN_ID_CNFL:
/* Command ID Conflict */
dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
"cmd ID conflict in cmd %p", (void *)cmd);
return (0);
case NVME_CQE_SC_GEN_INV_NS:
/* Invalid Namespace or Format */
if (!cmd->nc_dontpanic)
dev_err(cmd->nc_nvme->n_dip, CE_PANIC,
"programming error: invalid NS/format in cmd %p",
(void *)cmd);
return (EINVAL);
case NVME_CQE_SC_GEN_NVM_LBA_RANGE:
/* LBA Out Of Range */
dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
"LBA out of range in cmd %p", (void *)cmd);
return (0);
/*
* Non-fatal errors, handle gracefully.
*/
case NVME_CQE_SC_GEN_DATA_XFR_ERR:
/* Data Transfer Error (DMA) */
/* TODO: post ereport */
atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
return (EIO);
case NVME_CQE_SC_GEN_INTERNAL_ERR:
/*
* Internal Error. The spec (v1.0, section 4.5.1.2) says
* detailed error information is returned as async event,
* so we pretty much ignore the error here and handle it
* in the async event handler.
*/
atomic_inc_32(&cmd->nc_nvme->n_internal_err);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
return (EIO);
case NVME_CQE_SC_GEN_ABORT_REQUEST:
/*
* Command Abort Requested. This normally happens only when a
* command times out.
*/
/* TODO: post ereport or change blkdev to handle this? */
atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err);
return (ECANCELED);
case NVME_CQE_SC_GEN_ABORT_PWRLOSS:
/* Command Aborted due to Power Loss Notification */
ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
cmd->nc_nvme->n_dead = B_TRUE;
return (EIO);
case NVME_CQE_SC_GEN_ABORT_SQ_DEL:
/* Command Aborted due to SQ Deletion */
atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del);
return (EIO);
case NVME_CQE_SC_GEN_NVM_CAP_EXC:
/* Capacity Exceeded */
atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
return (EIO);
case NVME_CQE_SC_GEN_NVM_NS_NOTRDY:
/* Namespace Not Ready */
atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
return (EIO);
case NVME_CQE_SC_GEN_NVM_FORMATTING:
/* Format in progress (1.2) */
if (!NVME_VERSION_ATLEAST(&cmd->nc_nvme->n_version, 1, 2))
return (nvme_check_unknown_cmd_status(cmd));
atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_formatting);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
return (EIO);
default:
return (nvme_check_unknown_cmd_status(cmd));
}
}
static int
nvme_check_specific_cmd_status(nvme_cmd_t *cmd)
{
nvme_cqe_t *cqe = &cmd->nc_cqe;
switch (cqe->cqe_sf.sf_sc) {
case NVME_CQE_SC_SPC_INV_CQ:
/* Completion Queue Invalid */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE);
atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err);
return (EINVAL);
case NVME_CQE_SC_SPC_INV_QID:
/* Invalid Queue Identifier */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE ||
cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE ||
cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err);
return (EINVAL);
case NVME_CQE_SC_SPC_MAX_QSZ_EXC:
/* Max Queue Size Exceeded */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc);
return (EINVAL);
case NVME_CQE_SC_SPC_ABRT_CMD_EXC:
/* Abort Command Limit Exceeded */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT);
dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
"abort command limit exceeded in cmd %p", (void *)cmd);
return (0);
case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC:
/* Async Event Request Limit Exceeded */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT);
dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
"async event request limit exceeded in cmd %p",
(void *)cmd);
return (0);
case NVME_CQE_SC_SPC_INV_INT_VECT:
/* Invalid Interrupt Vector */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect);
return (EINVAL);
case NVME_CQE_SC_SPC_INV_LOG_PAGE:
/* Invalid Log Page */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE);
atomic_inc_32(&cmd->nc_nvme->n_inv_log_page);
return (EINVAL);
case NVME_CQE_SC_SPC_INV_FORMAT:
/* Invalid Format */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT);
atomic_inc_32(&cmd->nc_nvme->n_inv_format);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
return (EINVAL);
case NVME_CQE_SC_SPC_INV_Q_DEL:
/* Invalid Queue Deletion */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
atomic_inc_32(&cmd->nc_nvme->n_inv_q_del);
return (EINVAL);
case NVME_CQE_SC_SPC_NVM_CNFL_ATTR:
/* Conflicting Attributes */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT ||
cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
return (EINVAL);
case NVME_CQE_SC_SPC_NVM_INV_PROT:
/* Invalid Protection Information */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE ||
cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
atomic_inc_32(&cmd->nc_nvme->n_inv_prot);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
return (EINVAL);
case NVME_CQE_SC_SPC_NVM_READONLY:
/* Write to Read Only Range */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
atomic_inc_32(&cmd->nc_nvme->n_readonly);
if (cmd->nc_xfer != NULL)
bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
return (EROFS);
case NVME_CQE_SC_SPC_INV_FW_SLOT:
/* Invalid Firmware Slot */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_ACTIVATE);
return (EINVAL);
case NVME_CQE_SC_SPC_INV_FW_IMG:
/* Invalid Firmware Image */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_ACTIVATE);
return (EINVAL);
case NVME_CQE_SC_SPC_FW_RESET:
/* Conventional Reset Required */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_ACTIVATE);
return (0);
case NVME_CQE_SC_SPC_FW_NSSR:
/* NVMe Subsystem Reset Required */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_ACTIVATE);
return (0);
case NVME_CQE_SC_SPC_FW_NEXT_RESET:
/* Activation Requires Reset */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_ACTIVATE);
return (0);
case NVME_CQE_SC_SPC_FW_MTFA:
/* Activation Requires Maximum Time Violation */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_ACTIVATE);
return (EAGAIN);
case NVME_CQE_SC_SPC_FW_PROHIBITED:
/* Activation Prohibited */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_ACTIVATE);
return (EINVAL);
case NVME_CQE_SC_SPC_FW_OVERLAP:
/* Overlapping Firmware Ranges */
ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_FW_IMAGE_LOAD);
return (EINVAL);
default:
return (nvme_check_unknown_cmd_status(cmd));
}
}
static inline int
nvme_check_cmd_status(nvme_cmd_t *cmd)
{
nvme_cqe_t *cqe = &cmd->nc_cqe;
/*
* Take a shortcut if the controller is dead, or if
* command status indicates no error.
*/
if (cmd->nc_nvme->n_dead)
return (EIO);
if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS)
return (0);
if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC)
return (nvme_check_generic_cmd_status(cmd));
else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC)
return (nvme_check_specific_cmd_status(cmd));
else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY)
return (nvme_check_integrity_cmd_status(cmd));
else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR)
return (nvme_check_vendor_cmd_status(cmd));
return (nvme_check_unknown_cmd_status(cmd));
}
static int
nvme_abort_cmd(nvme_cmd_t *abort_cmd, uint_t sec)
{
nvme_t *nvme = abort_cmd->nc_nvme;
nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
nvme_abort_cmd_t ac = { 0 };
int ret = 0;
sema_p(&nvme->n_abort_sema);
ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid;
ac.b.ac_sqid = abort_cmd->nc_sqid;
cmd->nc_sqid = 0;
cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_cdw10 = ac.r;
/*
* Send the ABORT to the hardware. The ABORT command will return _after_
* the aborted command has completed (aborted or otherwise), but since
* we still hold the aborted command's mutex its callback hasn't been
* processed yet.
*/
nvme_admin_cmd(cmd, sec);
sema_v(&nvme->n_abort_sema);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
dev_err(nvme->n_dip, CE_WARN,
"!ABORT failed with sct = %x, sc = %x",
cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
atomic_inc_32(&nvme->n_abort_failed);
} else {
dev_err(nvme->n_dip, CE_WARN,
"!ABORT of command %d/%d %ssuccessful",
abort_cmd->nc_sqe.sqe_cid, abort_cmd->nc_sqid,
cmd->nc_cqe.cqe_dw0 & 1 ? "un" : "");
if ((cmd->nc_cqe.cqe_dw0 & 1) == 0)
atomic_inc_32(&nvme->n_cmd_aborted);
}
nvme_free_cmd(cmd);
return (ret);
}
/*
* nvme_wait_cmd -- wait for command completion or timeout
*
* In case of a serious error or a timeout of the abort command the hardware
* will be declared dead and FMA will be notified.
*/
static void
nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec)
{
clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC);
nvme_t *nvme = cmd->nc_nvme;
nvme_reg_csts_t csts;
nvme_qpair_t *qp;
ASSERT(mutex_owned(&cmd->nc_mutex));
while (!cmd->nc_completed) {
if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1)
break;
}
if (cmd->nc_completed)
return;
/*
* The command timed out.
*
* Check controller for fatal status, any errors associated with the
* register or DMA handle, or for a double timeout (abort command timed
* out). If necessary log a warning and call FMA.
*/
csts.r = nvme_get32(nvme, NVME_REG_CSTS);
dev_err(nvme->n_dip, CE_WARN, "!command %d/%d timeout, "
"OPC = %x, CFS = %d", cmd->nc_sqe.sqe_cid, cmd->nc_sqid,
cmd->nc_sqe.sqe_opc, csts.b.csts_cfs);
atomic_inc_32(&nvme->n_cmd_timeout);
if (csts.b.csts_cfs ||
nvme_check_regs_hdl(nvme) ||
nvme_check_dma_hdl(cmd->nc_dma) ||
cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) {
ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
nvme->n_dead = B_TRUE;
} else if (nvme_abort_cmd(cmd, sec) == 0) {
/*
* If the abort succeeded the command should complete
* immediately with an appropriate status.
*/
while (!cmd->nc_completed)
cv_wait(&cmd->nc_cv, &cmd->nc_mutex);
return;
}
qp = nvme->n_ioq[cmd->nc_sqid];
mutex_enter(&qp->nq_mutex);
(void) nvme_unqueue_cmd(nvme, qp, cmd->nc_sqe.sqe_cid);
mutex_exit(&qp->nq_mutex);
/*
* As we don't know what the presumed dead hardware might still do with
* the DMA memory, we'll put the command on the lost commands list if it
* has any DMA memory.
*/
if (cmd->nc_dma != NULL) {
mutex_enter(&nvme_lc_mutex);
list_insert_head(&nvme_lost_cmds, cmd);
mutex_exit(&nvme_lc_mutex);
}
}
static void
nvme_wakeup_cmd(void *arg)
{
nvme_cmd_t *cmd = arg;
mutex_enter(&cmd->nc_mutex);
cmd->nc_completed = B_TRUE;
cv_signal(&cmd->nc_cv);
mutex_exit(&cmd->nc_mutex);
}
static void
nvme_async_event_task(void *arg)
{
nvme_cmd_t *cmd = arg;
nvme_t *nvme = cmd->nc_nvme;
nvme_error_log_entry_t *error_log = NULL;
nvme_health_log_t *health_log = NULL;
nvme_nschange_list_t *nslist = NULL;
size_t logsize = 0;
nvme_async_event_t event;
/*
* Check for errors associated with the async request itself. The only
* command-specific error is "async event limit exceeded", which
* indicates a programming error in the driver and causes a panic in
* nvme_check_cmd_status().
*
* Other possible errors are various scenarios where the async request
* was aborted, or internal errors in the device. Internal errors are
* reported to FMA, the command aborts need no special handling here.
*
* And finally, at least qemu nvme does not support async events,
* and will return NVME_CQE_SC_GEN_INV_OPC | DNR. If so, we
* will avoid posting async events.
*/
if (nvme_check_cmd_status(cmd) != 0) {
dev_err(cmd->nc_nvme->n_dip, CE_WARN,
"!async event request returned failure, sct = %x, "
"sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct,
cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr,
cmd->nc_cqe.cqe_sf.sf_m);
if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) {
cmd->nc_nvme->n_dead = B_TRUE;
ddi_fm_service_impact(cmd->nc_nvme->n_dip,
DDI_SERVICE_LOST);
}
if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_OPC &&
cmd->nc_cqe.cqe_sf.sf_dnr == 1) {
nvme->n_async_event_supported = B_FALSE;
}
nvme_free_cmd(cmd);
return;
}
event.r = cmd->nc_cqe.cqe_dw0;
/* Clear CQE and re-submit the async request. */
bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t));
nvme_submit_admin_cmd(nvme->n_adminq, cmd);
switch (event.b.ae_type) {
case NVME_ASYNC_TYPE_ERROR:
if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) {
(void) nvme_get_logpage(nvme, B_FALSE,
(void **)&error_log, &logsize, event.b.ae_logpage);
} else {
dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
"async event reply: %d", event.b.ae_logpage);
atomic_inc_32(&nvme->n_wrong_logpage);
}
switch (event.b.ae_info) {
case NVME_ASYNC_ERROR_INV_SQ:
dev_err(nvme->n_dip, CE_PANIC, "programming error: "
"invalid submission queue");
return;
case NVME_ASYNC_ERROR_INV_DBL:
dev_err(nvme->n_dip, CE_PANIC, "programming error: "
"invalid doorbell write value");
return;
case NVME_ASYNC_ERROR_DIAGFAIL:
dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure");
ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
nvme->n_dead = B_TRUE;
atomic_inc_32(&nvme->n_diagfail_event);
break;
case NVME_ASYNC_ERROR_PERSISTENT:
dev_err(nvme->n_dip, CE_WARN, "!persistent internal "
"device error");
ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
nvme->n_dead = B_TRUE;
atomic_inc_32(&nvme->n_persistent_event);
break;
case NVME_ASYNC_ERROR_TRANSIENT:
dev_err(nvme->n_dip, CE_WARN, "!transient internal "
"device error");
/* TODO: send ereport */
atomic_inc_32(&nvme->n_transient_event);
break;
case NVME_ASYNC_ERROR_FW_LOAD:
dev_err(nvme->n_dip, CE_WARN,
"!firmware image load error");
atomic_inc_32(&nvme->n_fw_load_event);
break;
}
break;
case NVME_ASYNC_TYPE_HEALTH:
if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) {
(void) nvme_get_logpage(nvme, B_FALSE,
(void **)&health_log, &logsize, event.b.ae_logpage,
-1);
} else {
dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
"async event reply: %d", event.b.ae_logpage);
atomic_inc_32(&nvme->n_wrong_logpage);
}
switch (event.b.ae_info) {
case NVME_ASYNC_HEALTH_RELIABILITY:
dev_err(nvme->n_dip, CE_WARN,
"!device reliability compromised");
/* TODO: send ereport */
atomic_inc_32(&nvme->n_reliability_event);
break;
case NVME_ASYNC_HEALTH_TEMPERATURE:
dev_err(nvme->n_dip, CE_WARN,
"!temperature above threshold");
/* TODO: send ereport */
atomic_inc_32(&nvme->n_temperature_event);
break;
case NVME_ASYNC_HEALTH_SPARE:
dev_err(nvme->n_dip, CE_WARN,
"!spare space below threshold");
/* TODO: send ereport */
atomic_inc_32(&nvme->n_spare_event);
break;
}
break;
case NVME_ASYNC_TYPE_NOTICE:
switch (event.b.ae_info) {
case NVME_ASYNC_NOTICE_NS_CHANGE:
dev_err(nvme->n_dip, CE_NOTE,
"namespace attribute change event, "
"logpage = %x", event.b.ae_logpage);
atomic_inc_32(&nvme->n_notice_event);
if (event.b.ae_logpage != NVME_LOGPAGE_NSCHANGE)
break;
if (nvme_get_logpage(nvme, B_FALSE, (void **)&nslist,
&logsize, event.b.ae_logpage, -1) != 0) {
break;
}
if (nslist->nscl_ns[0] == UINT32_MAX) {
dev_err(nvme->n_dip, CE_CONT,
"more than %u namespaces have changed.\n",
NVME_NSCHANGE_LIST_SIZE);
break;
}
mutex_enter(&nvme->n_mgmt_mutex);
for (uint_t i = 0; i < NVME_NSCHANGE_LIST_SIZE; i++) {
uint32_t nsid = nslist->nscl_ns[i];
if (nsid == 0) /* end of list */
break;
dev_err(nvme->n_dip, CE_NOTE,
"!namespace nvme%d/%u has changed.",
ddi_get_instance(nvme->n_dip), nsid);
if (nvme_init_ns(nvme, nsid) != DDI_SUCCESS)
continue;
bd_state_change(
NVME_NSID2NS(nvme, nsid)->ns_bd_hdl);
}
mutex_exit(&nvme->n_mgmt_mutex);
break;
case NVME_ASYNC_NOTICE_FW_ACTIVATE:
dev_err(nvme->n_dip, CE_NOTE,
"firmware activation starting, "
"logpage = %x", event.b.ae_logpage);
atomic_inc_32(&nvme->n_notice_event);
break;
case NVME_ASYNC_NOTICE_TELEMETRY:
dev_err(nvme->n_dip, CE_NOTE,
"telemetry log changed, "
"logpage = %x", event.b.ae_logpage);
atomic_inc_32(&nvme->n_notice_event);
break;
case NVME_ASYNC_NOTICE_NS_ASYMM:
dev_err(nvme->n_dip, CE_NOTE,
"asymmetric namespace access change, "
"logpage = %x", event.b.ae_logpage);
atomic_inc_32(&nvme->n_notice_event);
break;
case NVME_ASYNC_NOTICE_LATENCYLOG:
dev_err(nvme->n_dip, CE_NOTE,
"predictable latency event aggregate log change, "
"logpage = %x", event.b.ae_logpage);
atomic_inc_32(&nvme->n_notice_event);
break;
case NVME_ASYNC_NOTICE_LBASTATUS:
dev_err(nvme->n_dip, CE_NOTE,
"LBA status information alert, "
"logpage = %x", event.b.ae_logpage);
atomic_inc_32(&nvme->n_notice_event);
break;
case NVME_ASYNC_NOTICE_ENDURANCELOG:
dev_err(nvme->n_dip, CE_NOTE,
"endurance group event aggregate log page change, "
"logpage = %x", event.b.ae_logpage);
atomic_inc_32(&nvme->n_notice_event);
break;
default:
dev_err(nvme->n_dip, CE_WARN,
"!unknown notice async event received, "
"info = %x, logpage = %x", event.b.ae_info,
event.b.ae_logpage);
atomic_inc_32(&nvme->n_unknown_event);
break;
}
break;
case NVME_ASYNC_TYPE_VENDOR:
dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event "
"received, info = %x, logpage = %x", event.b.ae_info,
event.b.ae_logpage);
atomic_inc_32(&nvme->n_vendor_event);
break;
default:
dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, "
"type = %x, info = %x, logpage = %x", event.b.ae_type,
event.b.ae_info, event.b.ae_logpage);
atomic_inc_32(&nvme->n_unknown_event);
break;
}
if (error_log != NULL)
kmem_free(error_log, logsize);
if (health_log != NULL)
kmem_free(health_log, logsize);
if (nslist != NULL)
kmem_free(nslist, logsize);
}
static void
nvme_admin_cmd(nvme_cmd_t *cmd, int sec)
{
mutex_enter(&cmd->nc_mutex);
nvme_submit_admin_cmd(cmd->nc_nvme->n_adminq, cmd);
nvme_wait_cmd(cmd, sec);
mutex_exit(&cmd->nc_mutex);
}
static void
nvme_async_event(nvme_t *nvme)
{
nvme_cmd_t *cmd;
cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
cmd->nc_sqid = 0;
cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT;
cmd->nc_callback = nvme_async_event_task;
cmd->nc_dontpanic = B_TRUE;
nvme_submit_admin_cmd(nvme->n_adminq, cmd);
}
static int
nvme_format_nvm(nvme_t *nvme, boolean_t user, uint32_t nsid, uint8_t lbaf,
boolean_t ms, uint8_t pi, boolean_t pil, uint8_t ses)
{
nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
nvme_format_nvm_t format_nvm = { 0 };
int ret;
format_nvm.b.fm_lbaf = lbaf & 0xf;
format_nvm.b.fm_ms = ms ? 1 : 0;
format_nvm.b.fm_pi = pi & 0x7;
format_nvm.b.fm_pil = pil ? 1 : 0;
format_nvm.b.fm_ses = ses & 0x7;
cmd->nc_sqid = 0;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_nsid = nsid;
cmd->nc_sqe.sqe_opc = NVME_OPC_NVM_FORMAT;
cmd->nc_sqe.sqe_cdw10 = format_nvm.r;
/*
* Some devices like Samsung SM951 don't allow formatting of all
* namespaces in one command. Handle that gracefully.
*/
if (nsid == (uint32_t)-1)
cmd->nc_dontpanic = B_TRUE;
/*
* If this format request was initiated by the user, then don't allow a
* programmer error to panic the system.
*/
if (user)
cmd->nc_dontpanic = B_TRUE;
nvme_admin_cmd(cmd, nvme_format_cmd_timeout);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
dev_err(nvme->n_dip, CE_WARN,
"!FORMAT failed with sct = %x, sc = %x",
cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
}
nvme_free_cmd(cmd);
return (ret);
}
/*
* The `bufsize` parameter is usually an output parameter, set by this routine
* when filling in the supported types of logpages from the device. However, for
* vendor-specific pages, it is an input parameter, and must be set
* appropriately by callers.
*/
static int
nvme_get_logpage(nvme_t *nvme, boolean_t user, void **buf, size_t *bufsize,
uint8_t logpage, ...)
{
nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
nvme_getlogpage_t getlogpage = { 0 };
va_list ap;
int ret;
va_start(ap, logpage);
cmd->nc_sqid = 0;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE;
if (user)
cmd->nc_dontpanic = B_TRUE;
getlogpage.b.lp_lid = logpage;
switch (logpage) {
case NVME_LOGPAGE_ERROR:
cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
*bufsize = MIN(NVME_VENDOR_SPECIFIC_LOGPAGE_MAX_SIZE,
nvme->n_error_log_len * sizeof (nvme_error_log_entry_t));
break;
case NVME_LOGPAGE_HEALTH:
cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
*bufsize = sizeof (nvme_health_log_t);
break;
case NVME_LOGPAGE_FWSLOT:
cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
*bufsize = sizeof (nvme_fwslot_log_t);
break;
case NVME_LOGPAGE_NSCHANGE:
cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
*bufsize = sizeof (nvme_nschange_list_t);
break;
default:
/*
* This intentionally only checks against the minimum valid
* log page ID. `logpage` is a uint8_t, and `0xFF` is a valid
* page ID, so this one-sided check avoids a compiler error
* about a check that's always true.
*/
if (logpage < NVME_VENDOR_SPECIFIC_LOGPAGE_MIN) {
dev_err(nvme->n_dip, CE_WARN,
"!unknown log page requested: %d", logpage);
atomic_inc_32(&nvme->n_unknown_logpage);
ret = EINVAL;
goto fail;
}
cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
}
va_end(ap);
getlogpage.b.lp_numd = *bufsize / sizeof (uint32_t) - 1;
cmd->nc_sqe.sqe_cdw10 = getlogpage.r;
if (nvme_zalloc_dma(nvme, *bufsize,
DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
dev_err(nvme->n_dip, CE_WARN,
"!nvme_zalloc_dma failed for GET LOG PAGE");
ret = ENOMEM;
goto fail;
}
if ((ret = nvme_fill_prp(cmd, cmd->nc_dma->nd_dmah)) != 0)
goto fail;
nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
dev_err(nvme->n_dip, CE_WARN,
"!GET LOG PAGE failed with sct = %x, sc = %x",
cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
goto fail;
}
*buf = kmem_alloc(*bufsize, KM_SLEEP);
bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
fail:
nvme_free_cmd(cmd);
return (ret);
}
static int
nvme_identify(nvme_t *nvme, boolean_t user, uint32_t nsid, uint8_t cns,
void **buf)
{
nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
int ret;
if (buf == NULL)
return (EINVAL);
cmd->nc_sqid = 0;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY;
cmd->nc_sqe.sqe_nsid = nsid;
cmd->nc_sqe.sqe_cdw10 = cns;
if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ,
&nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
dev_err(nvme->n_dip, CE_WARN,
"!nvme_zalloc_dma failed for IDENTIFY");
ret = ENOMEM;
goto fail;
}
if (cmd->nc_dma->nd_ncookie > 2) {
dev_err(nvme->n_dip, CE_WARN,
"!too many DMA cookies for IDENTIFY");
atomic_inc_32(&nvme->n_too_many_cookies);
ret = ENOMEM;
goto fail;
}
cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
if (cmd->nc_dma->nd_ncookie > 1) {
ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
&cmd->nc_dma->nd_cookie);
cmd->nc_sqe.sqe_dptr.d_prp[1] =
cmd->nc_dma->nd_cookie.dmac_laddress;
}
if (user)
cmd->nc_dontpanic = B_TRUE;
nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
dev_err(nvme->n_dip, CE_WARN,
"!IDENTIFY failed with sct = %x, sc = %x",
cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
goto fail;
}
*buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP);
bcopy(cmd->nc_dma->nd_memp, *buf, NVME_IDENTIFY_BUFSIZE);
fail:
nvme_free_cmd(cmd);
return (ret);
}
static int
nvme_set_features(nvme_t *nvme, boolean_t user, uint32_t nsid, uint8_t feature,
uint32_t val, uint32_t *res)
{
_NOTE(ARGUNUSED(nsid));
nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
int ret = EINVAL;
ASSERT(res != NULL);
cmd->nc_sqid = 0;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES;
cmd->nc_sqe.sqe_cdw10 = feature;
cmd->nc_sqe.sqe_cdw11 = val;
if (user)
cmd->nc_dontpanic = B_TRUE;
switch (feature) {
case NVME_FEAT_WRITE_CACHE:
if (!nvme->n_write_cache_present)
goto fail;
break;
case NVME_FEAT_NQUEUES:
break;
default:
goto fail;
}
nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
dev_err(nvme->n_dip, CE_WARN,
"!SET FEATURES %d failed with sct = %x, sc = %x",
feature, cmd->nc_cqe.cqe_sf.sf_sct,
cmd->nc_cqe.cqe_sf.sf_sc);
goto fail;
}
*res = cmd->nc_cqe.cqe_dw0;
fail:
nvme_free_cmd(cmd);
return (ret);
}
static int
nvme_get_features(nvme_t *nvme, boolean_t user, uint32_t nsid, uint8_t feature,
uint32_t *res, void **buf, size_t *bufsize)
{
nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
int ret = EINVAL;
ASSERT(res != NULL);
if (bufsize != NULL)
*bufsize = 0;
cmd->nc_sqid = 0;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_opc = NVME_OPC_GET_FEATURES;
cmd->nc_sqe.sqe_cdw10 = feature;
cmd->nc_sqe.sqe_cdw11 = *res;
/*
* For some of the optional features there doesn't seem to be a method
* of detecting whether it is supported other than using it. This will
* cause "Invalid Field in Command" error, which is normally considered
* a programming error. Set the nc_dontpanic flag to override the panic
* in nvme_check_generic_cmd_status().
*/
switch (feature) {
case NVME_FEAT_ARBITRATION:
case NVME_FEAT_POWER_MGMT:
case NVME_FEAT_TEMPERATURE:
case NVME_FEAT_ERROR:
case NVME_FEAT_NQUEUES:
case NVME_FEAT_INTR_COAL:
case NVME_FEAT_INTR_VECT:
case NVME_FEAT_WRITE_ATOM:
case NVME_FEAT_ASYNC_EVENT:
break;
case NVME_FEAT_WRITE_CACHE:
if (!nvme->n_write_cache_present)
goto fail;
break;
case NVME_FEAT_LBA_RANGE:
if (!nvme->n_lba_range_supported)
goto fail;
cmd->nc_dontpanic = B_TRUE;
cmd->nc_sqe.sqe_nsid = nsid;
ASSERT(bufsize != NULL);
*bufsize = NVME_LBA_RANGE_BUFSIZE;
break;
case NVME_FEAT_AUTO_PST:
if (!nvme->n_auto_pst_supported)
goto fail;
ASSERT(bufsize != NULL);
*bufsize = NVME_AUTO_PST_BUFSIZE;
break;
case NVME_FEAT_PROGRESS:
if (!nvme->n_progress_supported)
goto fail;
cmd->nc_dontpanic = B_TRUE;
break;
default:
goto fail;
}
if (user)
cmd->nc_dontpanic = B_TRUE;
if (bufsize != NULL && *bufsize != 0) {
if (nvme_zalloc_dma(nvme, *bufsize, DDI_DMA_READ,
&nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
dev_err(nvme->n_dip, CE_WARN,
"!nvme_zalloc_dma failed for GET FEATURES");
ret = ENOMEM;
goto fail;
}
if (cmd->nc_dma->nd_ncookie > 2) {
dev_err(nvme->n_dip, CE_WARN,
"!too many DMA cookies for GET FEATURES");
atomic_inc_32(&nvme->n_too_many_cookies);
ret = ENOMEM;
goto fail;
}
cmd->nc_sqe.sqe_dptr.d_prp[0] =
cmd->nc_dma->nd_cookie.dmac_laddress;
if (cmd->nc_dma->nd_ncookie > 1) {
ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
&cmd->nc_dma->nd_cookie);
cmd->nc_sqe.sqe_dptr.d_prp[1] =
cmd->nc_dma->nd_cookie.dmac_laddress;
}
}
nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
boolean_t known = B_TRUE;
/* Check if this is unsupported optional feature */
if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_FLD) {
switch (feature) {
case NVME_FEAT_LBA_RANGE:
nvme->n_lba_range_supported = B_FALSE;
break;
case NVME_FEAT_PROGRESS:
nvme->n_progress_supported = B_FALSE;
break;
default:
known = B_FALSE;
break;
}
} else {
known = B_FALSE;
}
/* Report the error otherwise */
if (!known) {
dev_err(nvme->n_dip, CE_WARN,
"!GET FEATURES %d failed with sct = %x, sc = %x",
feature, cmd->nc_cqe.cqe_sf.sf_sct,
cmd->nc_cqe.cqe_sf.sf_sc);
}
goto fail;
}
if (bufsize != NULL && *bufsize != 0) {
ASSERT(buf != NULL);
*buf = kmem_alloc(*bufsize, KM_SLEEP);
bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize);
}
*res = cmd->nc_cqe.cqe_dw0;
fail:
nvme_free_cmd(cmd);
return (ret);
}
static int
nvme_write_cache_set(nvme_t *nvme, boolean_t enable)
{
nvme_write_cache_t nwc = { 0 };
if (enable)
nwc.b.wc_wce = 1;
return (nvme_set_features(nvme, B_FALSE, 0, NVME_FEAT_WRITE_CACHE,
nwc.r, &nwc.r));
}
static int
nvme_set_nqueues(nvme_t *nvme)
{
nvme_nqueues_t nq = { 0 };
int ret;
/*
* The default is to allocate one completion queue per vector.
*/
if (nvme->n_completion_queues == -1)
nvme->n_completion_queues = nvme->n_intr_cnt;
/*
* There is no point in having more completion queues than
* interrupt vectors.
*/
nvme->n_completion_queues = MIN(nvme->n_completion_queues,
nvme->n_intr_cnt);
/*
* The default is to use one submission queue per completion queue.
*/
if (nvme->n_submission_queues == -1)
nvme->n_submission_queues = nvme->n_completion_queues;
/*
* There is no point in having more compeletion queues than
* submission queues.
*/
nvme->n_completion_queues = MIN(nvme->n_completion_queues,
nvme->n_submission_queues);
ASSERT(nvme->n_submission_queues > 0);
ASSERT(nvme->n_completion_queues > 0);
nq.b.nq_nsq = nvme->n_submission_queues - 1;
nq.b.nq_ncq = nvme->n_completion_queues - 1;
ret = nvme_set_features(nvme, B_FALSE, 0, NVME_FEAT_NQUEUES, nq.r,
&nq.r);
if (ret == 0) {
/*
* Never use more than the requested number of queues.
*/
nvme->n_submission_queues = MIN(nvme->n_submission_queues,
nq.b.nq_nsq + 1);
nvme->n_completion_queues = MIN(nvme->n_completion_queues,
nq.b.nq_ncq + 1);
}
return (ret);
}
static int
nvme_create_completion_queue(nvme_t *nvme, nvme_cq_t *cq)
{
nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
nvme_create_queue_dw10_t dw10 = { 0 };
nvme_create_cq_dw11_t c_dw11 = { 0 };
int ret;
dw10.b.q_qid = cq->ncq_id;
dw10.b.q_qsize = cq->ncq_nentry - 1;
c_dw11.b.cq_pc = 1;
c_dw11.b.cq_ien = 1;
c_dw11.b.cq_iv = cq->ncq_id % nvme->n_intr_cnt;
cmd->nc_sqid = 0;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE;
cmd->nc_sqe.sqe_cdw10 = dw10.r;
cmd->nc_sqe.sqe_cdw11 = c_dw11.r;
cmd->nc_sqe.sqe_dptr.d_prp[0] = cq->ncq_dma->nd_cookie.dmac_laddress;
nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
dev_err(nvme->n_dip, CE_WARN,
"!CREATE CQUEUE failed with sct = %x, sc = %x",
cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
}
nvme_free_cmd(cmd);
return (ret);
}
static int
nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx)
{
nvme_cq_t *cq = qp->nq_cq;
nvme_cmd_t *cmd;
nvme_create_queue_dw10_t dw10 = { 0 };
nvme_create_sq_dw11_t s_dw11 = { 0 };
int ret;
/*
* It is possible to have more qpairs than completion queues,
* and when the idx > ncq_id, that completion queue is shared
* and has already been created.
*/
if (idx <= cq->ncq_id &&
nvme_create_completion_queue(nvme, cq) != DDI_SUCCESS)
return (DDI_FAILURE);
dw10.b.q_qid = idx;
dw10.b.q_qsize = qp->nq_nentry - 1;
s_dw11.b.sq_pc = 1;
s_dw11.b.sq_cqid = cq->ncq_id;
cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
cmd->nc_sqid = 0;
cmd->nc_callback = nvme_wakeup_cmd;
cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE;
cmd->nc_sqe.sqe_cdw10 = dw10.r;
cmd->nc_sqe.sqe_cdw11 = s_dw11.r;
cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress;
nvme_admin_cmd(cmd, nvme_admin_cmd_timeout);
if ((ret = nvme_check_cmd_status(cmd)) != 0) {
dev_err(nvme->n_dip, CE_WARN,
"!CREATE SQUEUE failed with sct = %x, sc = %x",
cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
}
nvme_free_cmd(cmd);
return (ret);
}
static boolean_t
nvme_reset(nvme_t *nvme, boolean_t quiesce)
{
nvme_reg_csts_t csts;
int i;
nvme_put32(nvme, NVME_REG_CC, 0);
csts.r = nvme_get32(nvme, NVME_REG_CSTS);
if (csts.b.csts_rdy == 1) {
nvme_put32(nvme, NVME_REG_CC, 0);
for (i = 0; i != nvme->n_timeout * 10; i++) {
csts.r = nvme_get32(nvme, NVME_REG_CSTS);
if (csts.b.csts_rdy == 0)
break;
if (quiesce)
drv_usecwait(50000);
else
delay(drv_usectohz(50000));
}
}
nvme_put32(nvme, NVME_REG_AQA, 0);
nvme_put32(nvme, NVME_REG_ASQ, 0);
nvme_put32(nvme, NVME_REG_ACQ, 0);
csts.r = nvme_get32(nvme, NVME_REG_CSTS);
return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE);
}
static void
nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce)
{
nvme_reg_cc_t cc;
nvme_reg_csts_t csts;
int i;
ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT);
cc.r = nvme_get32(nvme, NVME_REG_CC);
cc.b.cc_shn = mode & 0x3;
nvme_put32(nvme, NVME_REG_CC, cc.r);
for (i = 0; i != 10; i++) {
csts.r = nvme_get32(nvme, NVME_REG_CSTS);
if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE)
break;
if (quiesce)
drv_usecwait(100000);
else
delay(drv_usectohz(100000));
}
}
/*
* Return length of string without trailing spaces.
*/
static int
nvme_strlen(const char *str, int len)
{
if (len <= 0)
return (0);
while (str[--len] == ' ')
;
return (++len);
}
static void
nvme_config_min_block_size(nvme_t *nvme, char *model, char *val)
{
ulong_t bsize = 0;
char *msg = "";
if (ddi_strtoul(val, NULL, 0, &bsize) != 0)
goto err;
if (!ISP2(bsize)) {