1f1540205fa6366266184180654434272c425ac2 - illumos-gate

commit	1f1540205fa6366266184180654434272c425ac2	[log] [tgz]
author	Robert Mustacchi <rm@joyent.com>	Sun Jul 15 16:02:36 2018 +0000
committer	Robert Mustacchi <rm@joyent.com>	Mon Sep 24 18:35:18 2018 +0000
tree	dbb354f00033a4b7c2db6b1ec88ba02ad977bf19
parent	856f620e96e5413932a6607aea5094db2ece172f [diff]

9820 Want risc-v disassembler
Reviewed by: Dan McDonald <danmcd@joyent.com>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Approved by: Garrett D'Amore <garrett@damore.org>

usr/src/cmd/dis/dis_main.c[diff]
usr/src/lib/libdisasm/Makefile.com[diff]
usr/src/lib/libdisasm/common/dis_riscv.c[Added - diff]
usr/src/lib/libdisasm/common/libdisasm.c[diff]
usr/src/lib/libdisasm/common/libdisasm.h[diff]
usr/src/pkg/manifests/system-test-utiltest.mf[diff]
usr/src/test/util-tests/tests/dis/Makefile[diff]
usr/src/test/util-tests/tests/dis/distest.ksh[diff]
usr/src/test/util-tests/tests/dis/risc-v-c/32.ldsr.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/32.ldsr.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/64.int.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/64.int.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/64.ldsr.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/64.ldsr.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/tst.int.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/tst.int.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/tst.ldsr.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v-c/tst.ldsr.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64a.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64a.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64d.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64d.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64f.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64f.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64i.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64i.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64m.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/64.rv64m.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.csr.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.csr.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.fpregs.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.fpregs.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.pseudo.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.pseudo.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.regs.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.regs.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32a.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32a.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32d.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32d.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32f.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32f.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32i.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32i.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32m.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.rv32m.s[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.supervisor.out[Added - diff]
usr/src/test/util-tests/tests/dis/risc-v/tst.supervisor.s[Added - diff]

48 files changed

tree: dbb354f00033a4b7c2db6b1ec88ba02ad977bf19