| /*- |
| * Copyright (c) 2006 M. Warner Losh. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * 1. Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * 2. Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| * |
| * This software is derived from software provide by Kwikbyte who specifically |
| * disclaimed copyright on the code. |
| * |
| * $FreeBSD$ |
| */ |
| |
| #ifndef __LIBAT91RM9200_H |
| #define __LIBAT91RM9200_H |
| |
| #include "at91rm9200.h" |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PMC_EnablePeriphClock |
| //* \brief Enable peripheral clock |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PMC_EnablePeriphClock ( |
| AT91PS_PMC pPMC, // \arg pointer to PMC controller |
| unsigned int periphIds) // \arg IDs of peripherals to enable |
| { |
| pPMC->PMC_PCER = periphIds; |
| } |
| |
| /* ***************************************************************************** |
| SOFTWARE API FOR PIO |
| ***************************************************************************** */ |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PIO_CfgPeriph |
| //* \brief Enable pins to be drived by peripheral |
| //*---------------------------------------------------------------------------- |
| static inline |
| void AT91F_PIO_CfgPeriph( |
| AT91PS_PIO pPio, // \arg pointer to a PIO controller |
| unsigned int periphAEnable, // \arg PERIPH A to enable |
| unsigned int periphBEnable) // \arg PERIPH B to enable |
| |
| { |
| if (periphAEnable) |
| pPio->PIO_ASR = periphAEnable; |
| if (periphBEnable) |
| pPio->PIO_BSR = periphBEnable; |
| pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode |
| } |
| |
| /* ***************************************************************************** |
| SOFTWARE API FOR MCI |
| ***************************************************************************** */ |
| //* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer |
| #define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) |
| |
| //* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A |
| #define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0) |
| |
| //* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B |
| #define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL) |
| |
| //* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A |
| #define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS ) |
| |
| //* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B |
| #define AT91C_MCI_SDCARD_4BITS_SLOTB (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS) |
| |
| |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_MCI_Configure |
| //* \brief Configure the MCI |
| //*---------------------------------------------------------------------------- |
| static inline |
| void AT91F_MCI_Configure( |
| AT91PS_MCI pMCI, // \arg pointer to a MCI controller |
| unsigned int DTOR_register, // \arg Data Timeout Register to be programmed |
| unsigned int MR_register, // \arg Mode Register to be programmed |
| unsigned int SDCR_register) // \arg SDCard Register to be programmed |
| { |
| //* Reset the MCI |
| pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN; |
| |
| //* Disable all the interrupts |
| pMCI->MCI_IDR = 0xFFFFFFFF; |
| |
| //* Set the Data Timeout Register |
| pMCI->MCI_DTOR = DTOR_register; |
| |
| //* Set the Mode Register |
| pMCI->MCI_MR = MR_register; |
| |
| //* Set the SDCard Register |
| pMCI->MCI_SDCR = SDCR_register; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_MCI_CfgPMC |
| //* \brief Enable Peripheral clock in PMC for MCI |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_MCI_CfgPMC(void) |
| { |
| AT91F_PMC_EnablePeriphClock( |
| AT91C_BASE_PMC, // PIO controller base address |
| ((unsigned int) 1 << AT91C_ID_MCI)); |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_MCI_CfgPIO |
| //* \brief Configure PIO controllers to drive MCI signals |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_MCI_CfgPIO(void) |
| { |
| // Configure PIO controllers to periph mode |
| AT91F_PIO_CfgPeriph( |
| AT91C_BASE_PIOA, // PIO controller base address |
| ((unsigned int) AT91C_PIO_PA28 ) | |
| ((unsigned int) AT91C_PIO_PA29 ) | |
| ((unsigned int) AT91C_PIO_PA27 ), // Peripheral A |
| 0); // Peripheral B |
| // Configure PIO controllers to periph mode |
| AT91F_PIO_CfgPeriph( |
| AT91C_BASE_PIOB, // PIO controller base address |
| 0, // Peripheral A |
| ((unsigned int) AT91C_PIO_PB5 ) | |
| ((unsigned int) AT91C_PIO_PB3 ) | |
| ((unsigned int) AT91C_PIO_PB4 )); // Peripheral B |
| } |
| |
| |
| /* ***************************************************************************** |
| SOFTWARE API FOR PDC |
| ***************************************************************************** */ |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_SetNextRx |
| //* \brief Set the next receive transfer descriptor |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_SetNextRx ( |
| AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
| char *address, // \arg address to the next bloc to be received |
| unsigned int bytes) // \arg number of bytes to be received |
| { |
| pPDC->PDC_RNPR = (unsigned int) address; |
| pPDC->PDC_RNCR = bytes; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_SetNextTx |
| //* \brief Set the next transmit transfer descriptor |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_SetNextTx( |
| AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
| char *address, // \arg address to the next bloc to be transmitted |
| unsigned int bytes) // \arg number of bytes to be transmitted |
| { |
| pPDC->PDC_TNPR = (unsigned int) address; |
| pPDC->PDC_TNCR = bytes; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_SetRx |
| //* \brief Set the receive transfer descriptor |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_SetRx( |
| AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
| char *address, // \arg address to the next bloc to be received |
| unsigned int bytes) // \arg number of bytes to be received |
| { |
| pPDC->PDC_RPR = (unsigned int) address; |
| pPDC->PDC_RCR = bytes; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_SetTx |
| //* \brief Set the transmit transfer descriptor |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_SetTx( |
| AT91PS_PDC pPDC, // \arg pointer to a PDC controller |
| char *address, // \arg address to the next bloc to be transmitted |
| unsigned int bytes) // \arg number of bytes to be transmitted |
| { |
| pPDC->PDC_TPR = (unsigned int) address; |
| pPDC->PDC_TCR = bytes; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_EnableTx |
| //* \brief Enable transmit |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_EnableTx( |
| AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
| { |
| pPDC->PDC_PTCR = AT91C_PDC_TXTEN; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_EnableRx |
| //* \brief Enable receive |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_EnableRx( |
| AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
| { |
| pPDC->PDC_PTCR = AT91C_PDC_RXTEN; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_DisableTx |
| //* \brief Disable transmit |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_DisableTx( |
| AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
| { |
| pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_DisableRx |
| //* \brief Disable receive |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_DisableRx( |
| AT91PS_PDC pPDC ) // \arg pointer to a PDC controller |
| { |
| pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; |
| } |
| |
| //*---------------------------------------------------------------------------- |
| //* \fn AT91F_PDC_Open |
| //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX |
| //*---------------------------------------------------------------------------- |
| static inline void |
| AT91F_PDC_Open( |
| AT91PS_PDC pPDC) // \arg pointer to a PDC controller |
| { |
| //* Disable the RX and TX PDC transfer requests |
| AT91F_PDC_DisableRx(pPDC); |
| AT91F_PDC_DisableTx(pPDC); |
| |
| //* Reset all Counter register Next buffer first |
| AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); |
| AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); |
| AT91F_PDC_SetTx(pPDC, (char *) 0, 0); |
| AT91F_PDC_SetRx(pPDC, (char *) 0, 0); |
| |
| //* Enable the RX and TX PDC transfer requests |
| AT91F_PDC_EnableRx(pPDC); |
| AT91F_PDC_EnableTx(pPDC); |
| } |
| |
| #endif |